How does always block add a latch

Hi ,
I have seen many implementations which say that the always block adds
an extra latch . BTW . what are the specific purposes of always_latch
and always_comb blocks from the designers perspective

 

[Jeremy Ralph]

parag_paul@hotmail.com wrote:

Hi ,
I have seen many implementations which say that the always block adds
an extra latch . BTW . what are the specific purposes of always_latch
and always_comb blocks from the designers perspective

Combinational logic (unclocked), sequential logic (clocked) and latched
logic (latches) can be inferred from an always block. As a rule many
design teams use only combinational and sequential blocks, hence
warnings when latches are inferred. Unless you really know what
you're doing latched logic is generally undesirable. If you get
latches for what should be a combinational block this is because your
description has some memory -- there is some logic path through your
always block in which every possible signal that can be driven from the
always block is not assigned a value.

As I understand it SystemVerilog has always_ff (sequential),
always_comb, always_latch so things can be defined more explicitly.
Anyone having positive/negative experiences with these more explicit
always blocks?

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps