How do you save a function result for infinity time?

[a_Conan]

Hi,

Suppose I have this code:
---------------------------------------
Function func_rt(
a : std_logic_vector(7 downto 0);
b : std_logic_vector(7 downto 0);
c : integer) return std_logic is
variable res : std_logic;
begin
res := a(c) and b(c)
return res;
end func_rt;
------------------------------------
----- main
..
..
Port( clock : in std_logic;
Rm : out std_logic)
..
..

Constant k1 : std_logic_vector(7 downto 0) := "10111010";
Constant k2 : std_logic_vector(7 downto 0) := "01111101";
..
..
Signal g : std_logic_vector(7 downto 0) : k1;
Signal f : std_logic_vector(7 downto 0) : k2;
Signal result : std_logic;
Signal ready : std_logic := '0';

Begin
Process(clock)
Begin
If(clock'event and clock = '1') then
If(Ready ='0') then
Result <= func_rt(g, f, 3);
Ready <= '1';
Else
Rm <= Result;
End if;
End process;
End program_behav;

-----------------------------
The problem when I run the program the upper code in the simulator can
give the result of signal 'Rm' = '1' very good. But when I use the
Quartus II syntheses tool to synthesize on the cyclone FPGA and I
assign the 'Rm' to the result the specific led gives nothing.
I think my problem that the next cycle of the process 'Result signal'
will be assigned to nothing, the Rm <= Result will get 'U' or 'Zero'.
Or anything.
The question is there any way to save the result of line:
Result <= func_rt(g, f, 3);
For infinity time, so I can use the Result Signal with newest value
anytime when the Ready signal became '1' .

 

[ajahn]

Well....usually default values for signals are not allowed for
synthesis. What you should do is add a reset to your process and let
the ready register reset to 0.
I would also use the rm signal directly as a register, if its not a
timing critical thing (you absolutely need the Rm signal to be one
clock delayed from the Result signal).
So for a LED-control I would write something like

P_LED_ctrl: PROCESS (clock, reset)
BEGIN -- PROCESS P_LED_ctrl
IF reset = '1' THEN --
asynchronous reset (active high)
ready <= '0';
Rm <= '0';
ELSIF clock'event AND clock = '1' THEN -- rising
clock edge
IF ready = '0' THEN
Rm <= func_rt(g, f, 3);
ready <= '1';
END IF;
END IF;
END PROCESS P_LED_ctrl;

I hope that helps...
Cheers,
Andreas.

 

[Duane Clark]

a_Conan wrote:

Hi,

Suppose I have this code:
---------------------------------------
Function func_rt(
a : std_logic_vector(7 downto 0);
b : std_logic_vector(7 downto 0);
c : integer) return std_logic is
variable res : std_logic;
begin
res := a(c) and b(c)
return res;
end func_rt;
------------------------------------
----- main
.
.
Port( clock : in std_logic;
Rm : out std_logic)
.
.

Constant k1 : std_logic_vector(7 downto 0) := "10111010";
Constant k2 : std_logic_vector(7 downto 0) := "01111101";
.
.
Signal g : std_logic_vector(7 downto 0) : k1;
Signal f : std_logic_vector(7 downto 0) : k2;
Signal result : std_logic;
Signal ready : std_logic := '0';

Begin
Process(clock)
Begin
If(clock'event and clock = '1') then
If(Ready ='0') then
Result <= func_rt(g, f, 3);
Ready <= '1';
Else
Rm <= Result;
End if;
End process;
End program_behav;

I am not familiar with Quartus FPGAs, so maybe this is not an issue. But
with most FPGAs, a big problem I can see here is that you need to think
about what happens when the FPGA powers up. Most FPGAs do not come out
of reset cleanly; that is, even Xilinx FPGAs have an asynchronous reset
on power up.

In your code, on coming out of reset, both Result and Ready are set on
the very first clock, and they are interdependent. That is likely to not
work right. Of course, if you don't care what the signals do at power
up, then this becomes a non issue. But that is one area where the
hardware may not be behaving like the simulation.

 

[a_Conan]

Thank you : ) it works