F
Frank
Guest
Since my simulator has different sets of test vectors which are of different
length.
As a result I declared a buffer of MAX_TV_LENGTH. Any switches in NCVerilog
to surpress this warning?
reg [2:0] bit_stream[0:`MAX_TV_LENGTH-1];
$readmem warning: words in file "../../cpp/input_slot0.dat" less than that
given by address bounds
$readmem warning: words in file "../../cpp/out_slot0.dat" less than that
given by address bounds
length.
As a result I declared a buffer of MAX_TV_LENGTH. Any switches in NCVerilog
to surpress this warning?
reg [2:0] bit_stream[0:`MAX_TV_LENGTH-1];
$readmem warning: words in file "../../cpp/input_slot0.dat" less than that
given by address bounds
$readmem warning: words in file "../../cpp/out_slot0.dat" less than that
given by address bounds