How do I read binary file data in a test bench?

[Pete Fraser]

Say I have a binary file containing compressed video.
I want to present the dut in my test bench with a byte
from the file at the dut's standard_logic_vector input,
every clock period.

What's the cleanest way to do this?
Can I use a binary file, or do I need to convert it to:

"xxxxxxxx"
"xxxxxxxx"
"xxxxxxxx"

with one 8-bit slv per line.

Is this simulator specific (I'll be using Modelim PE).

Thanks

 

[Pete Fraser]

"mike_treseler" <tres@fl_ke.com> wrote in message
news:63e5c6526ace7547cb933cc292546c84@localhost.talkaboutprogramming.com...

http://groups.google.com/groups?q=vhdl+sim+char_file

Thanks Mike.

Exactly the start I needed.

 

[Pete Fraser]

"mike_treseler" <tres@fl_ke.com> wrote in message
news:63e5c6526ace7547cb933cc292546c84@localhost.talkaboutprogramming.com...

http://groups.google.com/groups?q=vhdl+sim+char_file

-- Mike Treseler

That worked nicely, but I can't work out how to
convert from character to std_logic_vector.

test_sig <= conv_std_logic_vector(my_char_v, 8)
doesn't work.

The FAQ suggests it's possible, and gives some hints, but I still don't get
it.

Thanks

Pete

 

[Mike Treseler]

Pete Fraser wrote:

That worked nicely, but I can't work out how to
convert from character to std_logic_vector.

function char2std(arg:character)
return std_logic_vector is begin
return std_logic_vector(to_unsigned(character'pos(arg),8));
end char2std;

-- Mike Treseler

 

[mike_treseler]

http://groups.google.com/groups?q=vhdl+sim+char_file

-- Mike Treseler