How do I put LOC constraint on a coregen DPRAM?

[Kelvin @ SG]

Hi, group:

I am running core generator to make some dual port RAMs. However my design
involves partial reconfiguration, I need to put some LOC constraint on the
instantiated
DPRAMs, or at least find a way to confine the instance within an area group
of their
instantiator...How may I do that?

Kelvin

 

[Kelvin @ SG]

BTW, I am using Virtex-2 3000...and ISE6.1...

Thanks.
Kelvin



"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
news:c6ffap$4qr$1@reader01.singnet.com.sg...

Hi, group:

I am running core generator to make some dual port RAMs. However my design
involves partial reconfiguration, I need to put some LOC constraint on the
instantiated
DPRAMs, or at least find a way to confine the instance within an area
group
of their
instantiator...How may I do that?

Kelvin

 

[Symon]

Kelvin,
Use the floorplanner to find the name of your blockram after the translate
stage. Then add a LOC constraint in your UCF file. Read the 'Xilinx
constraints guide' to find out about the syntax, something like INST
"RTFM_BRAM" LOC = X0Y0;
HTH, Syms.