How do I perform RTL simulation with a Core Generator RAM an

[Student]

Hi, there:

How do I perform simulation with Core Generator module? Where can I find the
definition for BLKMEMDP_V5_0 anda MULT_GEN_V6_0?

Best Regards,
Kelvin

 

[Student]

Okie I got it...I found Core Gen manual...

Accidentally I generated DP-RAM in V5, but MULT in V6, will that hurt the
simulation or synthesis?
I use ISE 6.03i...

Kelvin




"Student" <student@nowhere.com> wrote in message
news:40a9c333$1@news.starhub.net.sg...

Hi, there:

How do I perform simulation with Core Generator module? Where can I find
the
definition for BLKMEMDP_V5_0 anda MULT_GEN_V6_0?

Best Regards,
Kelvin

 

[Peng Cong]

It will be OK
But it is better to use the newest version
"Student" <student@nowhere.com> Đ´ČëÓĘźţ
news:40a9c44c@news.starhub.net.sg...

Okie I got it...I found Core Gen manual...

Accidentally I generated DP-RAM in V5, but MULT in V6, will that hurt the
simulation or synthesis?
I use ISE 6.03i...

Kelvin




"Student" <student@nowhere.com> wrote in message
news:40a9c333$1@news.starhub.net.sg...
Hi, there:

How do I perform simulation with Core Generator module? Where can I find
the
definition for BLKMEMDP_V5_0 anda MULT_GEN_V6_0?

Best Regards,
Kelvin