How do i pass a real function to the output port

[shwetika]

module real_sin(x_in,sin_out);
input [63:0]x_in;
output wire [63:0] sin_out;
real r;

assign x=x_in;
assign r=sin(x_in);
assign sin_out=$realtobits(r);

function real sin(input real x);
real x1,y,y2,y3,y5,y7,sum,sign;

begin
sign = 1.0;
x1 = x;
if (x1<0)
begin
x1 = -x1;
sign = -1.0;
end
while (x1 > 3.14159265/2.0)
begin
x1 = x1 - 3.14159265;
sign = -1.0*sign;
end
y = x1*2/3.14159265;
y2 = y*y;
y3 = y*y2;
y5 = y3*y2;
y7 = y5*y2;
sum = 1.570794*y - 0.645962*y3 +
0.079692*y5 - 0.004681712*y7;
sin = sign*sum;

end
endfunction
endmodule

this piece of code gives me the following error
ERROR:HDLCompilers:246 - "real_sin.v" line 28 Reference to real
variable 'r' is not a legal net lvalue
ERROR:HDLCompilers:53 - "real_sin.v" line 28 Illegal left hand side of
continuous assign

I dont know a way around htis problem because each time i try a
different permutation and combination..the errors just keep increasing
specially "unsupported real or time function" errors.
Some kind of help and insight to make this code synthesize without
errors would be great!
Thanks,
Shwetika

 

[Kevin Neilson]

shwetika wrote:
....

this piece of code gives me the following error
ERROR:HDLCompilers:246 - "real_sin.v" line 28 Reference to real
variable 'r' is not a legal net lvalue
ERROR:HDLCompilers:53 - "real_sin.v" line 28 Illegal left hand side of
continuous assign

I dont know a way around htis problem because each time i try a
different permutation and combination..the errors just keep increasing
specially "unsupported real or time function" errors.
Some kind of help and insight to make this code synthesize without
errors would be great!
Thanks,
Shwetika

What tool are you using? I copied this into emacs and compiled it with
Modelsim and got no errors. You're not trying to synthesize, are you?
Synthesizers don't support reals. By the way, if you want a
nonsynthesizable sine function, instead of making your own Maclaurin
series you can just use the $sin() system function. This is a Verilog
2005 function which simulators should support. If your tools don't
support that, there are also some libraries on the web that will do
these transcendentals for you using CORDIC-style functions which get you
a bit more accuracy, I think.
-Kevin

 

On Jun 5, 4:51 pm, shwetika <shwetikaku...@gmail.com> wrote:

The problem that is causing the error is that you are assigning to a
variable with a continuous assignment. In Verilog (as opposed to
SystemVerilog), continuous assignments are only allowed to nets. And
there are no nets of type real. The easiest way to do this is to stop
storing the intermediate real values in variables and just do the
entire thing in one more complex expression. Vector input in, and
vector output out, and all operations done by applying function calls
to the results of function calls.

I also assume that your input is supposed to be a real value passed in
using a vector and $realtobits. So you need to convert it back to a
real before passing it to $sin. Otherwise it will get treated as a
large integer, and converted to the real number that is closest to
that integer, rather than the one that has the same bit
representation.