How do I judge the silicon area after place & route of ASIC

[Frank]

I was reading a paper, the author claimed algorithm A costs 60K gates, B
costs
80K gates after synthesis, however after P&R, B costs 6mm^2 while A costs
6mm^2.
Obviously B is better than A.

However, as a front end designer, how do I roughly judge the silicon area
of my
design after place & route?

 

[Mike Lewis]

"Frank" <Francis.invalid@hotmail.com> wrote in message
news:436ee651@news.starhub.net.sg...

I was reading a paper, the author claimed algorithm A costs 60K gates, B
costs
80K gates after synthesis, however after P&R, B costs 6mm^2 while A costs
6mm^2.
Obviously B is better than A.

However, as a front end designer, how do I roughly judge the silicon area
of my
design after place & route?

You should know your gate count before P&R, and as ssuch have an accurate
area reading. A "gate" is usually depicted as a 2 input NAND area
equivalent. 60K gates takes up 3/4 of the area of 80K gates and after P&R
that should still be true. I suppose that the sysnthesis for A had lousy
constraints and P&R beefed up the drive strength of the gates after
synthesis and as such the area was larger but if the appropriate constraints
were used that shouldn't happen.

Mike

 

[Frank]

I found another paper, which explains basically the same phenomenon.
I am sure it is not caused by constraints, but the author mentioned some
global wiring, since "earlier reports" used one computing unit while this
design uses two. Each computing unit takes 64-bit inputs from 1024
flipflops. Does the wiring make so much difference in routing?



Excerpt -------------------------
The synthesized cell areas of both
earlier reported architectures are approximately equivalent to
81 k inverter gates in our in-house technology. Compared to
those designs, the synthesized cell area of the present design
is equivalent to 123 k inverter gates. However, though the
cell area of the present design is about 34% higher than the
previous ones, the real advantage of the present one is visible
on the layout level. The core area of the present implementation
after layout is 6.8 mm2 , whereas the same parameter for the
referenced designs is approximately 18 mm2 for the same
technology. Thus, the present architecture exhibits superior
quality of silicon area utilization compared to the referenced
designs even though its cell area is higher.




"Mike Lewis" <someone@micrsoft.com> wrote in message
news:b96dnSAXeLIlUvLenZ2dnUVZ_tSdnZ2d@magma.ca...

"Frank" <Francis.invalid@hotmail.com> wrote in message
news:436ee651@news.starhub.net.sg...
I was reading a paper, the author claimed algorithm A costs 60K gates, B
costs
80K gates after synthesis, however after P&R, B costs 6mm^2 while A
costs
6mm^2.
Obviously B is better than A.

However, as a front end designer, how do I roughly judge the silicon
area
of my
design after place & route?




You should know your gate count before P&R, and as ssuch have an accurate
area reading. A "gate" is usually depicted as a 2 input NAND area
equivalent. 60K gates takes up 3/4 of the area of 80K gates and after P&R
that should still be true. I suppose that the sysnthesis for A had lousy
constraints and P&R beefed up the drive strength of the gates after
synthesis and as such the area was larger but if the appropriate
constraints
were used that shouldn't happen.

Mike

 

[Frank]

I found another paper, which explains basically the same phenomenon.
I am sure it is not caused by constraints, but the author mentioned some
global wiring, since "earlier reports" used one computing unit while this
design uses two. Each computing unit takes 64-bit inputs from 1024
flipflops. Does the wiring make so much difference in routing?



Excerpt -------------------------
The synthesized cell areas of both
earlier reported architectures are approximately equivalent to
81 k inverter gates in our in-house technology. Compared to
those designs, the synthesized cell area of the present design
is equivalent to 123 k inverter gates. However, though the
cell area of the present design is about 34% higher than the
previous ones, the real advantage of the present one is visible
on the layout level. The core area of the present implementation
after layout is 6.8 mm2 , whereas the same parameter for the
referenced designs is approximately 18 mm2 for the same
technology. Thus, the present architecture exhibits superior
quality of silicon area utilization compared to the referenced
designs even though its cell area is higher.




"Mike Lewis" <someone@micrsoft.com> wrote in message
news:b96dnSAXeLIlUvLenZ2dnUVZ_tSdnZ2d@magma.ca...

"Frank" <Francis.invalid@hotmail.com> wrote in message
news:436ee651@news.starhub.net.sg...
I was reading a paper, the author claimed algorithm A costs 60K gates, B
costs
80K gates after synthesis, however after P&R, B costs 6mm^2 while A
costs
6mm^2.
Obviously B is better than A.

However, as a front end designer, how do I roughly judge the silicon
area
of my
design after place & route?




You should know your gate count before P&R, and as ssuch have an accurate
area reading. A "gate" is usually depicted as a 2 input NAND area
equivalent. 60K gates takes up 3/4 of the area of 80K gates and after P&R
that should still be true. I suppose that the sysnthesis for A had lousy
constraints and P&R beefed up the drive strength of the gates after
synthesis and as such the area was larger but if the appropriate
constraints
were used that shouldn't happen.

Mike