How do I implement modulation by 12 in RTL?

[Mr. Ken]

My main counter is from 0~100000, but every 12 counts there is some
operation.
How best to implement this?

I have thought another counter with 0~11, but I like an alternative.

 

[John_H]

Mr. Ken wrote:

My main counter is from 0~100000, but every 12 counts there is some
operation.
How best to implement this?

I have thought another counter with 0~11, but I like an alternative.

One alternative would be to gate when bits [1:0] are 00 and bits [16:2]
are (count mod 3)==0. The way to get modulo 3 is to sum up the bit
pairs in a tree in a fashion similar to what you'd do to see if a
decimal number is divisible by 9.

For two binary pairs, you'd want the result to be modulo 3. The two-bit
values can give you a 3-bit result which you can again run through the
"moduloizer" to reduce to a 2-bit result. One lookup table can give you
the modulo-3 result for 2 bit pairs.

For either 4'hd or 4'h7, the two bit pairs decompose through a second
sum to give a modulo 3 result of 1:

2'h3 + 2'h1 == 3'h4 -> 1'h1 + 2'h0 == 2'h1

The fifteen MSbits of your 17-bit counter can go through four 4 input,
2-output function blocks which then feed 2 identical 4-input, 2-output
function blocks that then feed a single 4-input mod 3 == 0 check. You
would need 13 LUTs in an FPGA architecture to get the modulo-3 check.

Sound like fun? The same technique can be used for modulo 7, modulo 15,
modulo (2**n)-1.

 

[Mr. Ken]

"John_H" <newsgroup@johnhandwork.com> wrote in message
news:j92lh.10738$6Z5.9717@trndny01...

Mr. Ken wrote:
My main counter is from 0~100000, but every 12 counts there is some
operation.
How best to implement this?

I have thought another counter with 0~11, but I like an alternative.

One alternative would be to gate when bits [1:0] are 00 and bits [16:2]
are (count mod 3)==0. The way to get modulo 3 is to sum up the bit
pairs in a tree in a fashion similar to what you'd do to see if a
decimal number is divisible by 9.

For two binary pairs, you'd want the result to be modulo 3. The two-bit
values can give you a 3-bit result which you can again run through the
"moduloizer" to reduce to a 2-bit result. One lookup table can give you
the modulo-3 result for 2 bit pairs.

For either 4'hd or 4'h7, the two bit pairs decompose through a second
sum to give a modulo 3 result of 1:

2'h3 + 2'h1 == 3'h4 -> 1'h1 + 2'h0 == 2'h1

The fifteen MSbits of your 17-bit counter can go through four 4 input,
2-output function blocks which then feed 2 identical 4-input, 2-output
function blocks that then feed a single 4-input mod 3 == 0 check. You
would need 13 LUTs in an FPGA architecture to get the modulo-3 check.

Sound like fun? The same technique can be used for modulo 7, modulo 15,
modulo (2**n)-1.

Thank you John_H. Indeed it's good idea.

I guess with that kind of hardware and codes, I will get a 4-bit counter.