How do I do a serial input for a testbench

I have a logic design which can be intialized by a serial scan to a
port. I am having trouble getting a testbench set up to scan in the
initialization string. How do you do this? I would like to predefine a
string of 35 bits and then on each clock cycle present a bit of the
string to the input from position 0 to position 34... The define a new
string and repeat. Seems like this would be simple but I seem to be
missing something. I went looking for a testbench example but couldn't
find anything... Thanks

 

[michaelst@gmail.com]

Haven't tried it but should be something like that:

initial begin
send_string(35'h1234567);
send_string(35'h890abcd);
end

task send_string;
input [34:0] string;
begin
for(i=0;i<35;i=i+1) begin
@(posedge clk);
serial_out = string;
end
end
endtask

 

I out together the following test case and it worked, many many thanks.

serial_out needs to be declared as a reg not a wire, not sure why?

// Serial Testcase

`timescale 1 ns / 100 ps

module serial_testcase () ;

reg clk ;
integer i ;
reg serial_out ;

initial begin
send_string(8'b01011010);
end

always begin
clk <= 1; #10;
clk <= 0; #10;
end

task send_string;
input [7:0] string;
begin
for(i=0;i<8;i=i+1) begin
@(posedge clk);
serial_out = string;
end
end
endtask

endmodule