How do I declare subpackages?

[Derek Graham]

Hi

I want to organise my project into packages and subpackages but how do
I specify subpackages in VHDL?

For example, how would I declare this package hierarchy: a.b.c?

Would I need to declare the packages a and b first (in separate
files)?

Can I organise these package files into a matching directory
structure, like ~/a/b/c? (Similar to what Java does).

Thanks in advance,

Derek Graham

 

[Mike Treseler]

Derek Graham wrote

I want to organise my project into packages and subpackages but how do
I specify subpackages in VHDL?

Maybe you mean "entities containing multiple
processes and instances of other entities".

Packages and package bodies contain constants
and procedures called/used by one or more processes.
They are a way to share code, not a way
to structure design blocks.

Can I organise these package files into a matching directory
structure, like ~/a/b/c? (Similar to what Java does).

Not with packages.

VHDL sees design units only after they
are compiled. Compile order matters,
but the number of files does not.

Have a look at emacs vhdl-mode to organize your design.

-- Mike Treseler

 

[valentin tihomirov]

VHDL never mentiones nested packages. As advanced HDL develper never heard
of it, I think it is not supported. Furthermore, most of VHDL code is not
compiled into packages. Nestig of libraries is not supported as well I
beleive.

 

[Derek Graham]

I want to organise my project into packages and subpackages but how do
I specify subpackages in VHDL?

Maybe you mean "entities containing multiple
processes and instances of other entities".

Packages and package bodies contain constants
and procedures called/used by one or more processes.
They are a way to share code, not a way
to structure design blocks.

Hi Mike,

sorry, I wasn't very clear on what I meant as I was looking at it from
a Java perspective where you can organise closely related code into
packages (name spaces). I meant how do you organise code from a file
point of view rather than designs from a structural view? I realise
now that VDHL doesn't use packages for that purpose. I just find
putting all the code in one directory to be messy. I suppose I can
just alter the compiler's and simulator's arguments, which will be
difficult as I use Actel's Libero (which is a quite rubbish).

Can I organise these package files into a matching directory
structure, like ~/a/b/c? (Similar to what Java does).

Not with packages.

VHDL sees design units only after they
are compiled. Compile order matters,
but the number of files does not.

How do you organise your code/files??

Thanks for your help,

Derek

 

[Mike Treseler]

Derek Graham wrote:

Hi Mike,
I meant how do you organise code from a file
point of view rather than designs from a structural view? I realise
now that VHDL doesn't use packages for that purpose. I just find
putting all the code in one directory to be messy. I suppose I can
just alter the compiler's and simulator's arguments, which will be
difficult as I use Actel's Libero (which is a quite rubbish).

Yes. Take a look at emacs vhdl-mode.
That gives you lots of options on defining projects.
One or more directories, file lists, exclude regexps, etc.

You will get lots of opinions on this one.
I like to keep all the project source files in one directory
and sort things out with CVS, scripts and emacs speedbar.
Others will make good arguments for hierarchical directories.
I don't think there is a single correct answer.

-- Mike Treseler

 

[cristian]

I think the answer depends on the tool you are using to
synthesize/simulate your design.
There are tools that allow you to have a source directory for
instance. In that directory you can have all your source files. Of
course you will need to let the tool know the right path for the
files. The same for your testbenches. You can have a 'simulation'
directory. Even more some tools allow you to have 'external libraries'
(your onw libraries for instance).
I am not familiar with the software you mention, so I can not help
more. But, you should investigate the configuration options of your
tool.

 

[ivailokroumov]

Dear Derek,
I guess that you can't total organize your project with packades. Of
course, you can write packages and can use them, however this should be
usede when you want to share some information betweeen different ones
computers.
Best Regards:
Ivaylo Krumov

 

[valentin tihomirov]

I just find putting all the code in one directory to be messy.
How do you organise your code/files??

You can put your files wherever you like on you disk. Just tell the correct
compilation order to the simulator and synthesier.