How do I constrain this type of design?

[Kelvin @ SG]

Hi, there:

I am facing a complicated design with many internally generated clocks, see
below.

Now my problem is, when I define the clocks in UCF file,

ISE6 gave me warnings and remove all of the clocks from NGDBuildat the the
initialization
phase of partial reconfiguration design(meaning all black boxes for clk_gen,
a, b, & c).



Is this the correct behavior for partial reconfiguration design flow? I am
wondering how will the
final assembly work when all the clocks are removed.

Thank you very much for your ideas.

Best Regards,
Kelvin



##############################Constraints...
NET "internal_clock1_o" TNM_NET = "internal_clock1_o";
TIMESPEC "TS_internal_clock1_o" = PERIOD "internal_clock1_o" 1000 ns
HIGH 50 %;
NET "internal_clock2_o" TNM_NET = "internal_clock2_o";
TIMESPEC "TS_internal_clock2_o" = PERIOD "internal_clock2_o" 1000 ns
HIGH 50 %;
NET "internal_div_o" TNM_NET = "internal_div_o";
TIMESPEC "TS_internal_div_o" = PERIOD "internal_div_o" 2000 ns HIGH 50
%;
INST u_1 LOCK_PINS;
INST u_2 LOCK_PINS;
INST u_3 LOCK_PINS;
INST "u_1" LOC = "BUFGMUX7P";
INST "u_2" LOC = "BUFGMUX6S";
INST "u_3" LOC = "BUFGMUX1P";



/////////////////////////////////////////////Top level source code.

module my_top( clk, clk_gate1, clk_gate2, ... );

wire internal_clock1; // Gated
wire internal_clock2; // Gated
wire internal_div; // Divide by two

wire internal_clock1_o; // Gated
wire internal_clock2_o; // Gated
wire internal_div_o; // Divide by two

clk_gen( clk, clk_gate1, clk_gate2, clk_gate3, internal_clock1_o,
internal_clock_o, internal_div_o );

BUFGMUX u_1( .O(internal_clock1), ...); // Instantiate a clock buffer.
BUFGMUX u_2( .O(internal_clock2), ...); // Instantiate a clock buffer.
BUFGMUX u_3( .O(internal_div), ...); // Instantiate a clock buffer.

my_module1 a( internal_clock1, ........................);
my_module2 b( internal_clock2, ........................);
my_module3 c( internal_div, ........................);

endmodule









/////////////////////////////////////////////Warnings.....

Checking timing specifications ...
WARNING:XdmHelpers:625 - No instances driven from signal "internal_clock1_o"
are
valid for inclusion in TNM group "internal_clock1_o". A TNM property on a
pin
or signal marks only the flip-flops, latches and/or RAMs which are
directly
or indirectly driven by that pin or signal.
WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM
group
"internal_clock1_o". This group has been removed from the design.
WARNING:XdmHelpers:807 - The period specification "TS_internal_clock1_o" was
removed because the "internal_clock1_o" group was removed.



--
----------------------------------------------------------------
Xu Qijun
OKI Techno Centre (Singapore) Pte Ltd
TEL: 65-6770-7081 FAX:65-6779-2382
EMAIL: qijun677@oki.com
----------------------------------------------------------------
Warning: Although the company has taken reasonable precautions to ensure no
viruses are present in this email,
the company cannot accept responsibility for any loss or damage arising from
the use of this email or attachments.