S
Symon
Guest
Hi,
According to the Xilinx reference guides a TPSYNC timing point can be
attached to a net, macro pin, output or input pin of a primitive, or
an instance. I want to attach it to the 'D' input of a FF in my
design. Anyone know the UCF syntax for this?
Background is that I'm trying to constrain a path between two FFs in
different clock domains. One clock is from a DCM via a BUFG, the other
clock is from an input pad, using the normal routing fabric. So, just
using FFS to FFS in the two domains doesn't work because the timing
tool insists on a 'Clock Path Skew'. How it thinks it knows the skew
between two asynchronous clocks, I don't know! I can use MAXDELAY on
the nets, but this won't include Tcko or Tdick. Also, I used TPSYNC on
the 'from' instances to the FFS in the 'to' clock domain, but this
left out Tcko. So close!
Ta, Syms.
According to the Xilinx reference guides a TPSYNC timing point can be
attached to a net, macro pin, output or input pin of a primitive, or
an instance. I want to attach it to the 'D' input of a FF in my
design. Anyone know the UCF syntax for this?
Background is that I'm trying to constrain a path between two FFs in
different clock domains. One clock is from a DCM via a BUFG, the other
clock is from an input pad, using the normal routing fabric. So, just
using FFS to FFS in the two domains doesn't work because the timing
tool insists on a 'Clock Path Skew'. How it thinks it knows the skew
between two asynchronous clocks, I don't know! I can use MAXDELAY on
the nets, but this won't include Tcko or Tdick. Also, I used TPSYNC on
the 'from' instances to the FFS in the 'to' clock domain, but this
left out Tcko. So close!
Ta, Syms.