how do i add the two dimensional array to sensitivity list?

[news.singnet.com.sg]

Basically my design employees 16 pieces of 32-bit registers,

reg [31:0] temp_mem[0:15];

During writing to the memory, fine, I put it in a always @(clock)..
statement.

However during reading, I need it to be in a combinational circuit.

always @(temp_mem or read1 or read2 or read3 ...)

In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.

The reading is too complicated for a simple assign statement.

Any solutions?

 

On Nov 29, 7:38 am, "news.singnet.com.sg" <KEL8...@hotmaall.c0nn>
wrote:

Basically my design employees 16 pieces of 32-bit registers,

reg [31:0] temp_mem[0:15];

During writing to the memory, fine, I put it in a always @(clock)..
statement.

However during reading, I need it to be in a combinational circuit.

always @(temp_mem or read1 or read2 or read3 ...)

In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.

The reading is too complicated for a simple assign statement.

Any solutions?

If you are addressing it as memory, you can used just the address in
the sensitivity list. eg:
assign stuff = temp_mem[index];
always @ (index) ...

If you can (or need to) see all of the locations at once, you can
build a vector. eg:
assign vec = {temp_mem[0],temp_mem[1] ...}
always @ (vec) ...


G.

 

On Nov 29, 10:38 am, "news.singnet.com.sg" <KEL8...@hotmaall.c0nn>
wrote:

However during reading, I need it to be in a combinational circuit.

always @(temp_mem or read1 or read2 or read3 ...)

In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.

The reading is too complicated for a simple assign statement.

Any solutions?

The items in an event control must be valid expressions, because the
behavior of an event control is defined in terms of those expressions
changing value. An entire array is not a valid expression in Verilog,
so it is not legal to put an entire array in an event control. Even
in SystemVerilog where an entire array is legal as an expression in
certain contexts, it is still not legal in an event control.

You may be able to get what you want by using the Verilog-2001 @*
syntax. Technically, this is defined in terms of an equivalent event
control, and that equivalent event control would contain an entire
array, which is still illegal. So the meaning of @* is not defined as
something legal in this situation. However, implementations will
generally treat it the way you want: as sensitivity to all the
elements in the array. You will have to check whether your
implementation supports @*, and whether it will treat a reference to
an array in this way.

 

On Nov 29, 10:38 am, "news.singnet.com.sg" <KEL8...@hotmaall.c0nn>
wrote:

In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.

Any solutions?

The other way to do this would be to use a continuous assignment
instead of trying to use an always block. Continuous assignments were
designed to model combinational logic, and will automatically handle
array references properly. Always blocks were not really designed for
modeling combinational logic. You can make them do so, but you have
to handle the sensitivity yourself and you run into this problem with
arrays.

If you were using an always block because you needed procedural code,
you can get this in a continuous assignment by writing a function that
is used in the continuous assignment and contains your procedural
computation. However, the continuous assignment will assume that the
function represents a "pure" function that computes a combinational
result solely from its input arguments. If it is "impure" and uses
values other than its arguments as inputs, the continuous assignment
will not take that into account.

 

[ajcrm125]

On Nov 29, 10:38 am, "news.singnet.com.sg" <KEL8...@hotmaall.c0nn>
wrote:

Basically my design employees 16 pieces of 32-bit registers,

reg [31:0] temp_mem[0:15];

During writing to the memory, fine, I put it in a always @(clock)..
statement.

However during reading, I need it to be in a combinational circuit.

always @(temp_mem or read1 or read2 or read3 ...)

In Verilog I must write "always @(temp_mem[0] or temp_mem[1] or ... or read1
or read2 or read3 ...)
but I don't like the long list.

The reading is too complicated for a simple assign statement.

Any solutions?

I'm having a similar problem:

reg [0:10] MUX_RXWRD [0:`FIFO_DEPTH-1];
reg [0:10] S_RXWRD [0:`FIFO_DEPTH-1];
wire [0:`FIFIO_DEPTH-1] SHIFT;

always @(S_RXWRD or SHIFT)
begin
for (i=9;i<`FIFO_DEPTH;i=i+1)
MUX_RXWRD = (SHIFT) ? S_RXWRD[i+1] : S_RXWRD;
end

Because FIFO_DEPTH is definable, I can't declare a vector as described
above because I have no way on knowing just how big FIFO_DEPTH could
be.
Any ideas?

 

On Dec 7, 11:53 am, ajcrm125 <ajcrm...@gmail.com> wrote:

Because FIFO_DEPTH is definable, I can't declare a vector as described
above because I have no way on knowing just how big FIFO_DEPTH could
be.

Sure you can. Just define the width using an expression involving
FIFO_DEPTH.