How delicate is the output of a CMOS IC?

[pawihte]

Are standard CMOS logic ICs any more susceptible to damage from
external causes than BJT devices via the OUTput terminals? By
external causes, I mean things like ESD or a mild leakage current
from the mains supply.

As an example, suppose an output from a 4000 series logic gate is
intended to drive an external load, but may be left open at
times. Assume that it goes to the output terminal through a
series resistor (say a few kilohms as a buffer against capacitive
loads) but has no resistive path to ground when it's disconnected
from the load.

 

[Michael Black]

On Fri, 20 Nov 2009, pawihte wrote:

Are standard CMOS logic ICs any more susceptible to damage from
external causes than BJT devices via the OUTput terminals? By
external causes, I mean things like ESD or a mild leakage current
from the mains supply.

As an example, suppose an output from a 4000 series logic gate is
intended to drive an external load, but may be left open at
times. Assume that it goes to the output terminal through a
series resistor (say a few kilohms as a buffer against capacitive
loads) but has no resistive path to ground when it's disconnected
from the load.



No, the only way you'll damage it is if you end up loading it down

too much (like a short to ground, or by trying to supply too much current
to a following device), and that's not static related. I suppose maybe
a static discharge to the output might jump from the output to the input
and kill it that way, but that's a stretch.

The reason CMOS is static sensitive is because it has very high input
impedance. When static electricity hits that input, it's a tremendous
voltage at miniscule current, and that high voltage blows the input. But
if the input was loaded down a bit, it would so easily dissipate the high
voltage that the problem would go away.

Thus CMOS is at risk when it's just a stray IC. It may suffer in circuit,
if the input is left open to stray input, and no pullup or pulldown
resistor (though, that case is less likely to happen since you don't want
to leave CMOS inputs open since you then can't rely on the output to be a
specific state).

The outputs of CMOS aren't so static sensitive, at the very least they
are by nature loaded down by the complementary MOS transistor, so there
is finite impedance to any CMOS output.

Michael

 

[pawihte]

Michael Black wrote:

On Fri, 20 Nov 2009, pawihte wrote:

Are standard CMOS logic ICs any more susceptible to damage
from
external causes than BJT devices via the OUTput terminals? By
external causes, I mean things like ESD or a mild leakage
current
from the mains supply.

As an example, suppose an output from a 4000 series logic gate
is
intended to drive an external load, but may be left open at
times. Assume that it goes to the output terminal through a
series resistor (say a few kilohms as a buffer against
capacitive
loads) but has no resistive path to ground when it's
disconnected
from the load.



No, the only way you'll damage it is if you end up loading it
down
too much (like a short to ground, or by trying to supply too
much
current to a following device), and that's not static related.

Yes. That's why I have the series resistor at the output, to
serve double duty as a load current limiter *and* for stability
with capacitive loads (it's a low-speed circuit that I have not
yet constructed or even fully designed).

I suppose maybe a static discharge to the output might jump
from the output to the
input and kill it that way, but that's a stretch.

That /is/ stretching it. I suppose I could make doubly sure by

placing bleed resistors between the several output points and
ground. After all, resistors cost next to nothing, but I dislike
unnecessary clutter.

The reason CMOS is static sensitive is because it has very high
input
impedance. When static electricity hits that input, it's a
tremendous
voltage at miniscule current, and that high voltage blows the
input. But if the input was loaded down a bit, it would so
easily dissipate
the high voltage that the problem would go away.

Thus CMOS is at risk when it's just a stray IC. It may suffer
in
circuit, if the input is left open to stray input, and no
pullup or
pulldown resistor (though, that case is less likely to happen
since
you don't want to leave CMOS inputs open since you then can't
rely on
the output to be a specific state).

The inputs are properly terminated.

The outputs of CMOS aren't so static sensitive, at the very
least they
are by nature loaded down by the complementary MOS transistor,
so
there is finite impedance to any CMOS output.

Thought so, but I wanted confirmation in case there was some

aspect I hadn't thought of. Thanks for the reply.

 

[Rich Grise]

On Sat, 21 Nov 2009 01:51:57 +0530, pawihte wrote:

Michael Black wrote:
On Fri, 20 Nov 2009, pawihte wrote:

Are standard CMOS logic ICs any more susceptible to damage from
external causes than BJT devices via the OUTput terminals? By external
causes, I mean things like ESD or a mild leakage current
from the mains supply.
....
The outputs of CMOS aren't so static sensitive, at the very least they
are by nature loaded down by the complementary MOS transistor, so there
is finite impedance to any CMOS output.

Thought so, but I wanted confirmation in case there was some aspect I
hadn't thought of. Thanks for the reply.

If you're paranoid, you could put a couple of 1N4148's or 1N914's to
Vdd and ground, "downstream" of your load limiting resistor.

Cheers!
Rich

 

[EHWollmann]

"pawihte" <pawihte@invalid.com> wrote in message news:he6dcc$lad$1@news.eternal-september.org...

Are standard CMOS logic ICs any more susceptible to damage from
external causes than BJT devices via the OUTput terminals? By
external causes, I mean things like ESD or a mild leakage current
from the mains supply.

As an example, suppose an output from a 4000 series logic gate is
intended to drive an external load, but may be left open at
times. Assume that it goes to the output terminal through a
series resistor (say a few kilohms as a buffer against capacitive
loads) but has no resistive path to ground when it's disconnected
from the load.