How could I get LUT-level netlist in Xilinx ISE?

C

chifalcon

Guest
Hi, I need to convert the high level design to LUT level netlist, and the
make corrections to it.

In a paper, author says:

"The translate step generates a Verilog netlist that can easily be parsed
This netlist consists out of declarations of primitive modules of th
device"

The netlist is shown as following:

******************************************
...
defparam LUT_37.INIT = 16'hC800;
//synthesis attribute HU_SET of LUT_37 is "SLICE_37";
//synthesis attribute rloc of LUT_37 is "X0Y0";
X_LUT4 LUT37 (.ADR0(n7), .ADR1(n4), .ADR2(n3), .ADR3(n, .o(n41);
....

******************************************
I searched all the files in the project folder, but didn't find this kin
of netlist.

I just want to know how to get this kind of netlist in Xilinx FPGA?

Thanks very much!!



---------------------------------------
Posted through http://www.FPGARelated.com
 
On 06/02/2011 09:56 AM, chifalcon wrote:
Hi, I need to convert the high level design to LUT level netlist, and then
make corrections to it.

Why? Wouldn't you rather correct the high level design once, then make
Click to expand...
correct LUT level netlists every time you use it? Otherwise you're
doomed to hand-correcting that netlist every time you synthesize, or
you're stuck with that low-level netlist instead of a nice readable,
portable, etc., high level design.

The only valid reason I see to do this is if you have to hand-optimize
the placement of some really timing-critical piece of IP, and even there
it would seem that you could go far with careful use of timing
constraints. But you wouldn't be doing that at the LUT level anyway,
would you?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
Tim Wescott <tim@seemywebsite.com> wrote:
On 06/02/2011 09:56 AM, chifalcon wrote:
Hi, I need to convert the high level design to LUT level netlist, and then
make corrections to it.

Why? Wouldn't you rather correct the high level design once, then make
correct LUT level netlists every time you use it? Otherwise you're
doomed to hand-correcting that netlist every time you synthesize, or
you're stuck with that low-level netlist instead of a nice readable,
portable, etc., high level design.
Click to expand...
In the XC4000 days, I had a design that used Xilinx (RPM) macros,
similar to the way people call assembly programs from a high-level
language to do things that the compiler won't do. The way it was
done was to generate a dummy (empty) module in verilog, generate
the netlist based on that, then remove the generated netlist file
at the appropriate place just before P&R and supply the RPM to P&R.

I believe it is still possible to do something similar.

The only valid reason I see to do this is if you have to hand-optimize
the placement of some really timing-critical piece of IP, and even there
it would seem that you could go far with careful use of timing
constraints. But you wouldn't be doing that at the LUT level anyway,
would you?
Click to expand...
Or maybe to work around a bug in the tools.

-- glen
 
Hi, Thanks for your reply.
I am working on the security of cryptography. Some related work cannot b
done by regular synthesize way.
I am generating the DRP logic (Dual Rail with Precharge logic). I need t
transform the sigle-ended circuit (normal circuit) to the complementar
dual rail circuit.
This cannot be directly done by the existing synthesis tool, just lik
XST. BY far, the only possible way to do it is manually correcting the LU
netlist or manually modify on FPGA editor.

Best,


On 06/02/2011 09:56 AM, chifalcon wrote:
Hi, I need to convert the high level design to LUT level netlist, an
then
make corrections to it.

Why? Wouldn't you rather correct the high level design once, then make
correct LUT level netlists every time you use it? Otherwise you're
doomed to hand-correcting that netlist every time you synthesize, or
you're stuck with that low-level netlist instead of a nice readable,
portable, etc., high level design.

The only valid reason I see to do this is if you have to hand-optimize
the placement of some really timing-critical piece of IP, and even there
it would seem that you could go far with careful use of timing
constraints. But you wouldn't be doing that at the LUT level anyway,
would you?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi, Thank you!

It really helpful! I will try it tomorrow!

Best,


Hi,

What you describe looks like simulation netlist. You can generate it
using Xilinx netgen tool either in command-line mode or from ISE
(generate post-synthesis simulation model).

Thanks,
Evgeni
http://outputlogic.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi,

What you describe looks like simulation netlist. You can generate it
using Xilinx netgen tool either in command-line mode or from ISE
(generate post-synthesis simulation model).

Thanks,
Evgeni
http://outputlogic.com
 
"chifalcon" <eric.he@n_o_s_p_a_m.hotmail.com> writes:

Hi, I need to convert the high level design to LUT level netlist, and then
make corrections to it.
Click to expand...
XDL is a textual representation of the lowest level of FPGA that is easy to get
to (FPGA Editor level: slices, PIPs, wires...).

You can then hack on that to your heart's content and (in theory at least) turn
it back into an NCD file and then on to a bitstream.

Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
 
Yes, I was doing on XDL for a long time. But the problem is : If I work o
XDL, I have to seperate the original core and complementary core. In othe
words, they are placed independently. So they are dual-core, but dual-rai
logic.

The ideal way is to placed the dual parts together. This means each pair o
original and complementary LUT are placed in the same SLICE. In XDL, th
position for each LUT has already been located in the specific hardwar
resources. There is no free neighbouring hardware to place th
complementary LUT. Therefore, I have to work on a kind o
no-hardware-specific LUT netlist.

I am still checking..

Best,


"chifalcon" <eric.he@n_o_s_p_a_m.hotmail.com> writes:

Hi, I need to convert the high level design to LUT level netlist, an
then
make corrections to it.

XDL is a textual representation of the lowest level of FPGA that is eas
to get
to (FPGA Editor level: slices, PIPs, wires...).

You can then hack on that to your heart's content and (in theory at least
turn
it back into an NCD file and then on to a bitstream.

Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
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