how can I set outputs high on startup?

[Matt Clement]

Hey Guys/Gals,

I have a design that needs 32 outputs to be started or asynchronously set to
high right after power up. I also have two clocked state machine processes
which run and act on those 32 outputs. I have tried just about everything I
can think of to get it to work. The closest I got was going to a dummy
state initially and setting them to high, but this of course requires a
clock prior to setting them high. I would like to set them high without
having to wait for a clock pulse. Here is a section of how I tried to use a
reset to set them to one and then output a 1 on the reset to ensure I dont
satisfy that condition again....doesnt work :-(

Please let me know if you see something I am missing. I tried to use the
STATE signal to do a conditional statement to set them while in S37 and that
did not work either.





ENTITY HALF_CLONE IS
PORT
(CLK : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADD : IN STD_LOGIC_VECTOR(5 DOWNTO 1);
DAT : OUT STD_LOGIC;
LED1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
BUTTONS : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RESET : INOUT STD_LOGIC
);

END HALF_CLONE;

ARCHITECTURE ONE OF HALF_CLONE IS
TYPE STATE_TYPE IS
(S37,IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34,S35,S36,S38,S39);
SIGNAL STATE1: STATE_TYPE;
SIGNAL STATE: STATE_TYPE;
SIGNAL TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0);


BEGIN


PROCESS (clk, ADD)
VARIABLE DATA : STD_LOGIC_VECTOR(32 DOWNTO 0); --was 35




BEGIN

IF (RESET = '0') THEN --also tried IF (STATE = S37) THEN
LED1<="11111111111111111111111111111111";
--STATE<=IDLE;



ELSIF (CLK'EVENT AND CLK = '1') THEN

CASE STATE IS


WHEN IDLE =>



IF SEL(7 downto 2) = (ADD(5 DOWNTO 1) & '1') THEN
--DATA(35):=SEL(1);
STATE<=S0;
ELSE
STATE<=IDLE;
END IF;


........and so forth.

 

[Ben Jones]

Hi Matt,

"Matt Clement" <clement@nanotechsys.com> wrote in message
news:Iwzdh.1053$4p2.521@trndny07...

Hey Guys/Gals,

I have a design that needs 32 outputs to be started or asynchronously set
to high right after power up. I also have two clocked state machine
processes which run and act on those 32 outputs. I have tried just about
everything I can think of to get it to work. The closest I got was going
to a dummy state initially and setting them to high, but this of course
requires a clock prior to setting them high. I would like to set them
high without having to wait for a clock pulse.

PROCESS (clk, ADD)
VARIABLE DATA : STD_LOGIC_VECTOR(32 DOWNTO 0); --was 35
BEGIN
IF (RESET = '0') THEN --also tried IF (STATE = S37) THEN
LED1<="11111111111111111111111111111111";
--STATE<=IDLE;

Ugh, too loud.

Your main problem is that the process isn't sensitive to the reset signal,
so it doesn't see its value until ADD or CLK changes. What you probably
meant was

process(clk, reset)
variable data : std_logic_vector(32 downto 0);
begin
if reset = '0' then
led1 <= (others => '1');
elsif rising_edge(clock) then
case state is
when idle =>
...
end case;
end if;
end process;

I don't see why it should need to be sensitive to ADD either.

Cheers,

-Ben-

 

[Matt Clement]

Thanks Ben for your response

You are correct the ADD was supposed to be Reset but even then, the process
is only started on a clock cycle or a change on reset. I dont have a way of
changing the reset value. I was using the reset as an INOUT so that I
could change it within the system rather than externally. I just tried
making a seperate process that uses a wait statement like below to try and
set the LED1 outputs and it gives an error that it creates constant drivers
for net LED1.

process
begin
wait until reset = '0';
led1<="11111111111111111111111111111111";
reset<='1';
end process;



"Ben Jones" <ben.jones@xilinx.com> wrote in message
news:el6h9c$dbt3@cnn.xsj.xilinx.com...

Hi Matt,

"Matt Clement" <clement@nanotechsys.com> wrote in message
news:Iwzdh.1053$4p2.521@trndny07...
Hey Guys/Gals,

I have a design that needs 32 outputs to be started or asynchronously set
to high right after power up. I also have two clocked state machine
processes which run and act on those 32 outputs. I have tried just about
everything I can think of to get it to work. The closest I got was going
to a dummy state initially and setting them to high, but this of course
requires a clock prior to setting them high. I would like to set them
high without having to wait for a clock pulse.

PROCESS (clk, ADD)
VARIABLE DATA : STD_LOGIC_VECTOR(32 DOWNTO 0); --was 35
BEGIN
IF (RESET = '0') THEN --also tried IF (STATE = S37) THEN
LED1<="11111111111111111111111111111111";
--STATE<=IDLE;

Ugh, too loud.

Your main problem is that the process isn't sensitive to the reset signal,
so it doesn't see its value until ADD or CLK changes. What you probably
meant was

process(clk, reset)
variable data : std_logic_vector(32 downto 0);
begin
if reset = '0' then
led1 <= (others => '1');
elsif rising_edge(clock) then
case state is
when idle =
...
end case;
end if;
end process;

I don't see why it should need to be sensitive to ADD either.

Cheers,

-Ben-

 

[Ben Jones]

Hi Matt,

"Matt Clement" <clement@nanotechsys.com> wrote in message
news:hqAdh.2108$g_3.1442@trndny02...

Thanks Ben for your response

You are correct the ADD was supposed to be Reset but even then, the
process is only started on a clock cycle or a change on reset. I dont
have a way of changing the reset value. I was using the reset as an
INOUT so that I could change it within the system rather than externally.

No, don't do that.

You probably want a new "led1_internal" signal to hold the values being
driven during normal operation, and then outside your synchronous process
you can put some gates to drive it to all-ones when the reset is asserted.
Something like this:

led1 <= led1_internal when reset = '0' else (others => '1');

process(clock, reset)
begin
if reset='1' then
elsif rising_edge(clock) then
--... fiddle around with led1_internal and other signals
end if;
end process;

Note that your module's output will then no longer be driven by a register;
it will come from combinatorial logic instead, which may cause you timing
problems.

If this is a question of power-up sequencing, then you may want to check the
manual for the device and tool-chain you are using, and see if there is a
mechanism for doing what you want more cleanly. Most FPGAs and CPLDs will
allow you to specify a power-on initial value for your signals by means of
an initial value assignment in VHDL, or maybe an attribute.

Good luck,

-Ben-