How can I make it in the real chip??

[Lee]

Hello,

I am writing verilog code for an IP core. In my current code, the
input is feed into at the first clock cycle. But the output can't be
ready at the first cycle and it will be ready at the fourth clock
cycle.

In the real chip, how to deal with this in order to cooperate with
other chip in the same PCB board?Give some output signals and they can
indicate when the output is ready?

Tell me the good way to solve this kind of problem,please.

Thanks,

 

[Swapnajit Mittra]

yxl4444@louisiana.edu (Lee) wrote in message news:<5c3c88bc.0406271456.64a511e6@posting.google.com>...

Hello,

I am writing verilog code for an IP core. In my current code, the
input is feed into at the first clock cycle. But the output can't be
ready at the first cycle and it will be ready at the fourth clock
cycle.

In the real chip, how to deal with this in order to cooperate with
other chip in the same PCB board?Give some output signals and they can
indicate when the output is ready?

Tell me the good way to solve this kind of problem,please.

Thanks,

Yes, you will have another signal that will be asserted when the
output is valid. In popular lingo, your processed output is called
'data', and the control signal that tells about the validity of
'data' is called 'data valid.' Note that 'data valid' is a control
signal.

In a little more complicated scenario, if you have output data
coming out in a different order than the input stream, you also
need to 'tag' the corresponding input and the output data phases.
This is done using another control signal, whose popular name
is - you guessed it - 'tag.'

- Swapnajit.
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.project-veripage.com/

 

[Just an Illusion]

Hi,

If you don't want use two signal, you can think about tri-state signal
usage.
That doesn't give you a wait to informe other component; but if all
other block known that they must wait at least 4 clock cycle between
request and data disponibility, you are safe.

An other idea, it seems that you have the problem only at start, haven't
you ? Why don't include a top register to inhibate any communication
before 4 clock cycle after the reset ? In that wait, your ip can be well
initialize before any communication.

JaI

Lee wrote:

Hello,

I am writing verilog code for an IP core. In my current code, the
input is feed into at the first clock cycle. But the output can't be
ready at the first cycle and it will be ready at the fourth clock
cycle.

In the real chip, how to deal with this in order to cooperate with
other chip in the same PCB board?Give some output signals and they can
indicate when the output is ready?

Tell me the good way to solve this kind of problem,please.

Thanks,