How can I get an output clock phased align with the input cl

C

chris

Guest
Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.
 
Hi Chris,

Basically you need a controllable skew on your clock domain
distributed over the PCB, right?
What is the master clock frequency and where is it derived from?
I might have a solution based on this info.

Regards, Luc
On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote:

Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.
Click to expand...
 
ccoutand@hotmail.com (chris) wrote in news:33923a80.0406020327.20fde6f3
@posting.google.com:

Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.
Click to expand...

Can't you just use two DCMs as shown in the FPGA datasheet to remove the
skew caused by the buffer and PCB delays?



--
----------------------------------------------------------------
Dr. Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com
 
Take a look at Xilinx App Note 174 - Figure 11 (Board Level
Deskew of Board Level Clock between Multiple FPGAs.

The jist is that after your master FPGA generates its output clock
at the PWB level, the signal is routed back into the FPGA BUFG
input and is used to drive the FB input of the originating DLL/DCM.
This is parallel for the Master FPGA as well as slaves.

Traces should be matched at the board level. Also, make sure you
think about the reset philosophy of the multiple FPGAs on the board.
This usually requires a little thought, since resets and clock availability
are tightly coupled in synchronous design. Usually, the master FPGA
also distributes a "reset" signal to apply to slave DLLs.

--
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

Colorado based Xilinx Design consultant

email : jretta@rtc-inc.com
web : www.rtc-inc.com


"chris" <ccoutand@hotmail.com> wrote in message
news:33923a80.0406020327.20fde6f3@posting.google.com...
Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.
Click to expand...
 
Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<5dfrb05arvko4ndjhikh2fat7b2c28mdis@4ax.com>...
Hi Chris,

Basically you need a controllable skew on your clock domain
distributed over the PCB, right?
What is the master clock frequency and where is it derived from?
I might have a solution based on this info.

Regards, Luc
On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote:

Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.
Click to expand...
Hi Luc,

The master clock frequency is around 100MHz and is coming from an ADC.

Christophe.
 
Chris,

Do you need other frequencies in your FPGAs derived from this clock?
Is it single ended or differential?
What skew do you need to anticipate?

PLease let me know,

Luc

On 3 Jun 2004 00:56:08 -0700, ccoutand@hotmail.com (chris) wrote:

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<5dfrb05arvko4ndjhikh2fat7b2c28mdis@4ax.com>...
Hi Chris,

Basically you need a controllable skew on your clock domain
distributed over the PCB, right?
What is the master clock frequency and where is it derived from?
I might have a solution based on this info.

Regards, Luc
On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote:

Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.

Hi Luc,

The master clock frequency is around 100MHz and is coming from an ADC.

Christophe.
Click to expand...
 
Hi Christophe,

Look on the Lattice website. They have released the part that I
mentioned before.
Look under clock management. Very easy interface, a lot of features,
flexible profile management, etc.

Best regards,

Luc

On 2 Jun 2004 04:27:18 -0700, ccoutand@hotmail.com (chris) wrote:

Hi,

I have several FPGAs in my design and I want the first FPGA to feed
the other FPGAs with its master clock. The first FPGA use a DCM to
reshape an input clock and get its master clock.
I want the three FPGAs to have a phase-aligned clock.
I just don't know how to do it since the master clock of the first
FPGA which is the output clk0 of the DCM has to go through an output
buffer to access a pin to be distributed to the others FPGAs but then
the clock would have a delay compare to clk0.
Is someone can help me with that ?

Thanks. Christophe.
Click to expand...
 
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