how can I drive an array from a component to the top level ?

[yossi]

I have a question related to my design,

I have a component that has lots of registers (120 registers 8bit each).
In this case I can declare an Array in side this component.
my quaestion is:
can I drive it out of this component to the top level?

I was trying to do that with no success, can you assist?


ENTITY registers IS
PORT (

my_array out -- .....??

);
END;

 

[yossi]

On Thursday, August 2, 2012 1:09:33 PM UTC+3, yossi wrote:

I have a question related to my design,



I have a component that has lots of registers (120 registers 8bit each).

In this case I can declare an Array in side this component.

my quaestion is:

can I drive it out of this component to the top level?



I was trying to do that with no success, can you assist?





ENTITY registers IS

PORT (



my_array out -- .....??



);

END;

hello everybody
Can somebody assist?

 

[Andy]

On Thursday, August 2, 2012 5:09:33 AM UTC-5, yossi wrote:

I have a question related to my design, I have a component that has lots of registers (120 registers 8bit each). In this case I can declare an Array in side this component. my quaestion is: can I drive it out of this component to the top level? I was trying to do that with no success, can you assist? ENTITY registers IS PORT ( my_array out -- .....?? ); END;

You can drive the array out on a port just fine, but you have to declare the type for the array (and therefore, the port) in a package that is invoked by not only the entity, but also the calling architecture and anything else that needs to declare a signal/variable or port of this type.

Andy

 

[Anton Gunman]

Hello,

You can do it as such:
------------------------------------------------------------
-- my_pkg.vhd
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

package my_pkg is
-- Array dimensions
constant ARRAY_SIZE : integer := 120;
constant REG_WIDTH : integer := 8;

-- Array type declaration
type my_array_type is array (0 to ARRAY_SIZE-1) of std_logic_vector(REG_WIDTH-1 downto 0);

end package my_pkg;

------------------------------------------------------------
-- registers.vhd
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.my_pkg.all; -- Package (array declaration)

entity registers is

port (
--...
my_array_out : out my_array_type);
end registers;
--...