How can I deal with the output signal in testbech?

[Devlin]

hello:
I have a small count design, which I want to do functional simlation
in modelsim. the code are following;
module count4(cnt,clk)
output [3:0] cnt;
input clk;
reg [3:0] cnt;

always@(posedge clk)
cnt = cnt +1;
endmodule


This is just a 4 bits simple counter design. and I do not have the
reset signal in it.(just for test).
you see that the modelsim treat "cnt" as x at initial time, so the
result can not be right.
So I want to modify the cnt signal in testbench, I done as follows:


initial
force cnt = 0;
#500 release cnt;


and the clk is 100.
but the reesult is not right either.
My question is : How can I make the cnt to be a specific value in
testbench?
just not using the reset or preset, thanks.

 

[Srinivasan Venkataramanan]

Try doing the force from inside your module level, i.e. if you counnt4
was instantiated in testbench as:

module tb;
count4 dut (.*);

initial begin : b1
force dut.cnt = 0;
#500 release dut.cnt
end : b1
endmodule : tb

HTH
Ajeetha, CVC
www.noveldv.com

P.S. I have used some SystemVerilog syntax though not absolutely needed
for this example.

 

[Devlin]

thank you very much!!
It really works!
But could you explain a little more for doing this.
Why should force the cnt from the module level but not the top ?

 

[Devlin]

I think I got it. thanks
just to understand what is drvier.

 

[Ajeetha]

Delvin,
Sorry, just got back to this forum. Yes it is an issue with
multiple drivers when you forced from outside.

Ajeetha, CVC
www.noveldv.com