how can I clock double - or how can I avoid loosing clocks

[Reza Naima]

I've written some code that is supposed to drive an SPI bus in a very
simple way - just clock out 16 bits and then toggle the chip select.
However, the code I've written manages to only run at 1/2 the clock
speed that the cpld is running at. If you notice, the always block
will toggle the sck line on only the posege of clk_in. And I can't
modify the always block to run at the posedge and negedge of clk_in.

After much googling, I've come up with an idea, but I'm not sure if
it's viable. If I take the clk_in, and split the signal, sending 1/2
of it through many gates (doesn't matter what) so it would add a delay,
then xor-ing with it's original signal, I should get 2x the input
frequency but with a very non 50% duty cycle. If I then use that to
trigger the always block, I should recover the original frequency.

Thoughts? Will this work? Is there a better way to do this?

Thanks,
Reza

module DA_Driver(reset, clk_in, sck, cs);

input reset;

/* SPI Related */
input clk_in;
output sck;
output cs;
reg cs;
reg sck;
reg [4:0] spi_counter;


/* cs toggler */
always @(posedge reset or posedge clk_in) begin
if (reset) begin
spi_counter <= 0;
cs <= 0;
sck <= 0;
end else begin
sck <= !sck;
spi_counter <= spi_counter + 1;
if (spi_counter == 16)
cs <= 1;
if (spi_counter == 17) begin
cs <= 0;
spi_counter <= 0;
end
end
end


endmodule

 

[Rob]

The code you wrote only manages to run at 1/2 the input clock speed because
that is exactly what you've asked the synthesizer to implement.

Your data must be clocked out from another module because I don't see any
data being clocked out from this module. What are you driving with the
sclk? Why don't you drive what ever sclk is tied to directly with the
system clock and just use this module to toggle your cs?


"Reza Naima" <google@reza.net> wrote in message
news:1140824097.349286.72420@i39g2000cwa.googlegroups.com...

I've written some code that is supposed to drive an SPI bus in a very
simple way - just clock out 16 bits and then toggle the chip select.
However, the code I've written manages to only run at 1/2 the clock
speed that the cpld is running at. If you notice, the always block
will toggle the sck line on only the posege of clk_in. And I can't
modify the always block to run at the posedge and negedge of clk_in.

After much googling, I've come up with an idea, but I'm not sure if
it's viable. If I take the clk_in, and split the signal, sending 1/2
of it through many gates (doesn't matter what) so it would add a delay,
then xor-ing with it's original signal, I should get 2x the input
frequency but with a very non 50% duty cycle. If I then use that to
trigger the always block, I should recover the original frequency.

Thoughts? Will this work? Is there a better way to do this?

Thanks,
Reza

module DA_Driver(reset, clk_in, sck, cs);

input reset;

/* SPI Related */
input clk_in;
output sck;
output cs;
reg cs;
reg sck;
reg [4:0] spi_counter;


/* cs toggler */
always @(posedge reset or posedge clk_in) begin
if (reset) begin
spi_counter <= 0;
cs <= 0;
sck <= 0;
end else begin
sck <= !sck;
spi_counter <= spi_counter + 1;
if (spi_counter == 16)
cs <= 1;
if (spi_counter == 17) begin
cs <= 0;
spi_counter <= 0;
end
end
end


endmodule