HOT NWELL problems with assura

Hello everybody,

I am currently writing my diploma thesis and have this problem i
couldn't solve.
I use the ASSURA version 3.16 with an AMS HIT-KIT 3.70. When I check
the layout
with DIVA there is NO problem, but checking with ASSURA I get the
warning:
hot nwell.

Then I build a simple PMOS transistor and get the problem too. The
NWELL is connected to
VDD. Could anybody tell me a hint?

THANKS!

Best Regards
Florian

 

[Kholdoun TORKI]

Hi Florian,

This is an ERC (Electrical Rule Checking) not available in
the Diva deck file.
Hot nwell means that your NWELL is not polarized to the power supply,
(or to a voltage larger or equal to the source of the PMOS).

1) You need to connect your NWELL to VDD by making an NTAP.
(Look at one of the standard-cells from CORELIB.)

2) You need to put a label on layer (PIN, Mx) on the METx connected to
this NTAP. This label can be any string containing the following
substrings :
VDD or VCC or vdd or vcc.

Mx can be M1, M2, M3 or M4, respectively with MET1, MET2, MET3 or MET4.

Regards,

==================
Kholdoun TORKI
CMP
http://cmp.imag.fr
===================

mimirsbrun@web.de wrote:

Hello everybody,

I am currently writing my diploma thesis and have this problem i
couldn't solve.
I use the ASSURA version 3.16 with an AMS HIT-KIT 3.70. When I check
the layout
with DIVA there is NO problem, but checking with ASSURA I get the
warning:
hot nwell.

Then I build a simple PMOS transistor and get the problem too. The
NWELL is connected to
VDD. Could anybody tell me a hint?

THANKS!

Best Regards
Florian