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Hi,
the following task is from a homework:
Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.
Now my question:
How can a process create something?
Hi,
the following task is from a homework:
Write a synthesis-compliant process that creates 10 clock-edge-controlled
flipflops using asynchonous reset.
Now my question:
How can a process create something?
TIA
Bryan
Tee hee. Great Mysteries of the Universe, #37: Howthe following task is from a homework:
Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.
Now my question:
How can a process create something?
Thank you for your answer.On Thu, 06 Jul 2006 12:33:41 GMT, Bryan Johnson <bs@bsnet.com> wrote:
Hi,
the following task is from a homework:
Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.
Now my question:
How can a process create something?
Within an entity, a process can create almost anything.
For instance:
process(some_signal,clock)
begin
if some_signal='0' then
output<'0';
elsif rising_edge(clock) then
output<='1';
end if;
end process;
Completing this process with all necessary headers, you will have a
process that "creates" a single flip_flop with asynchronous active-low
reset, and fed back so that it will toggle on every clock edge.
Once you understand it , you will be perfectly able to do your
homework.
Zara
Maybe this is a solution:
....
It is not wrong, but usually vectors are defined in downward directionentity flipflop10 is
port (
reset, clock : in std_logic;
d_in : in std_logic_vector(1 to 10);
d_out : out std_logic_vector(1 to 10));
end entity;
No. If you want to make the next step in learning VHDL you could have aOr am I missing something here?
Hi Ralf,No. If you want to make the next step in learning VHDL you could have a
look at the for-generate statement.
gen_label : for N in 0 to 9 generate
-- code for a single flipflop d_out(N) inside
-- that selects d_in(N)
end generate;
In your 1st question it is not mentioned, that a for-generate orgen_label : for N in 0 to 9 generate
-- code for a single flipflop d_out(N) inside
-- that selects d_in(N)
end generate;
I know of the for-generate statement.
But can it be used inside a process, as my
homework question (see first post) says?
On 06.07.2006 16:56, * Ralf Hildebrandt wrote:
No. If you want to make the next step in learning VHDL you could have a
look at the for-generate statement.
gen_label : for N in 0 to 9 generate
-- code for a single flipflop d_out(N) inside
-- that selects d_in(N)
end generate;
Hi Ralf,
I know of the for-generate statement.
But can it be used inside a process, as my
homework question (see first post) says?
I don't think this makes sense.
Bryan
On Thu, 06 Jul 2006 12:33:41 GMT, Bryan Johnson <bs@bsnet.com> wrote:
the following task is from a homework:
Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.
Now my question:
How can a process create something?
Tee hee. Great Mysteries of the Universe, #37: How
can a homework problem do anything useful?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Humbug. The whole of Usenet is "unnecessary". The directlyIf you do want to answer the question then please do not answer it but
do not pass unnecssary remarks.
which nicely challenges the kind of sloppy wording (and,How can a process create something?