home to pass unix variable into ncverilog testbench

[junk_no_spam]

Is there any way to pass a Unix variable, say $test_number,
into the testbench, as a ncverilog command line switch?

I want to do something inside the testbench like:

inital
begin
if ( test_number == 1 )
variable = 1
if ( test_number == 2 )
variable = 0
if ( test_number == 3 )
variable = 0
: :
: :
: :
end


-steve

 

[Jeremy Ralph]

If I recall correctly you can:

1) use the +define+ invoation option, which would go something like the
following:
ncverilog ... +define+test_number=$test_number ...
Then in your testbench use `test_number (with the tick) in place of
test_number as you had written.

-or-

2) add the +test_number invoation option... something like:
ncverilog ... +test_number=$test_number ...
Then in your tb use $value$plusargs("test_number=%d", test_number)

Hope this helps,
Jeremy

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps


junk_no_spam wrote:

Is there any way to pass a Unix variable, say $test_number,
into the testbench, as a ncverilog command line switch?

I want to do something inside the testbench like:

inital
begin
if ( test_number == 1 )
variable = 1
if ( test_number == 2 )
variable = 0
if ( test_number == 3 )
variable = 0
: :
: :
: :
end


-steve

 

junk_no_spam wrote:

Is there any way to pass a Unix variable, say $test_number,
into the testbench, as a ncverilog command line switch?

As Jeremy suggested, you could use the -define option to ncvlog (or the
+define option to ncverilog) to set a macro value, using the Unix
variable in the command line to get the shell to substitute the value
in the command line passed to the executable. One problem with this is
that it requires recompiling the design.

If the change you are making does not require any structural changes to
the design, you should not need to recompile the design. Your example
qualifies, since you are just testing the value in if-statements at
runtime. In this case, you can use your own plusarg on the ncsim
command line (or the ncverilog command line, assuming it is smart
enough not to recompile when you change the options). Then you can
read an associated value from the command line in your Verilog code
using the Verilog-2001 $value$plusarg() system function. For example,
you could use the command line

ncsim +test_number=$test_number mydesign

Then in your Verilog code, you can write

integer test_number;

initial begin
if ($value$plusargs("test_number=%d", test_number) == 0)
$display("No test number given");
if (test_number == 1)
...