Hold violations

[a2zasics]

Hi,
I have an Altera FPGA, which shows hold violation on an input pin. The
first FLOP is positive edge triggered and in IOB. To get rid of the
roughly 2 ns margin in hold, i put -3ns phase shift in clock output of
PLL that clocks the input register. Apparently this was ignored in
hold time calculation. Can someone point out why ? A negative shift in
clock should have made hold time better in this case.

Shardendu

 

[Vaughn Betz]

shardendu@verizon.net (a2zasics) wrote in message news:<1c97c9ba.0312081405.1013564b@posting.google.com>...

Hi,
I have an Altera FPGA, which shows hold violation on an input pin. The
first FLOP is positive edge triggered and in IOB. To get rid of the
roughly 2 ns margin in hold, i put -3ns phase shift in clock output of
PLL that clocks the input register. Apparently this was ignored in
hold time calculation. Can someone point out why ? A negative shift in
clock should have made hold time better in this case.

Shardendu

Hi Shardendu,

Which Altera FPGA are you using? You are right that shifting your
clock backward should help the hold problem. It's hard to say what's
going on here without seeing your design -- if you send it to me, or a
small test case showing the problem behaviour, I can have someone look
at it.

One thing to check: make sure you've set a Th = 0 constraint on this
register if that's the constraint you want met. Without a constraint
like that, Quartus won't be trying to ensure you get a 0 or negative
hold time.

Vaughn
Altera