Hold value on tristate (not trireg)

[Kenneth Brun Nielsen]

Hi,

I have a multiple-driver bus featuring tri-state. Any ideas to how I
can hold values while the bus is tristated? I.e. when no driver drives
the bus, I want it to hold the last data value.

I'm simulating in Icarus, and Icarus does NOT feature the trireg
datatype - any ideas for an alternative implementation?

Best regards,
Kenneth

 

[Jonathan Bromley]

On May 14, 10:15 am, Kenneth Brun Nielsen wrote:

I have a multiple-driver bus featuring tri-state. Any ideas to how I
can hold values while the bus is tristated? I.e. when no driver drives
the bus, I want it to hold the last data value.

I'm simulating in Icarus, and Icarus does NOT feature the trireg
datatype - any ideas for an alternative implementation?

You can easily fake up trireg for simulation by adding
a behavioural equivalent of the usual "weak keeper" circuit:

assign (weak0, weak1) the_bus = the_bus;

Capacitive decay is a little trickier, and is left as an
exercise for the reader
--
Jonathan Bromley

 

[Kenneth Brun Nielsen]

On May 14, 12:45 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On May 14, 10:15 am, Kenneth Brun Nielsen wrote:

I have a multiple-driver bus featuring tri-state. Any ideas to how I
can hold values while the bus is tristated? I.e. when no driver drives
the bus, I want it to hold the last data value.

I'm simulating in Icarus, and Icarus does NOT feature the trireg
datatype - any ideas for an alternative implementation?

You can easily fake up trireg for simulation by adding
a behavioural equivalent of the usual "weak keeper" circuit:

  assign (weak0, weak1) the_bus = the_bus;

It works! Thanks a lot, Jonathan.

Best regards,
Kenneth

 

[Terry Ou]

On 5月14日, 上午6時45分, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

You can easily fake up trireg for simulation by adding
a behavioural equivalent of the usual "weak keeper" circuit:

  assign (weak0, weak1) the_bus = the_bus;

Capacitive decay is a little trickier, and is left as an
exercise for the reader
--
Jonathan Bromley

Hi,
Since for the trireg, it can only be used in the behavior verilog.
Is there any suggestion how to do this actually?
It probably can be done by adding a small keeper, but any better idea?
Thanks,
Terry

 

[Bernd Paysan]

Terry Ou wrote:

Hi,
Since for the trireg, it can only be used in the behavior verilog.
Is there any suggestion how to do this actually?
It probably can be done by adding a small keeper, but any better idea?

If you want to synthesize that stuff, yes, adding a small keeper (basically
a buffer with weak drivers) is the right way to go.

--
Bernd Paysan
"If you want it done right, you have to do it yourself!"
http://www.jwdt.com/~paysan/