hlp_needed in VHDL

[vicky]

Hi All,

i'm new to VHDL, my aim is to overload airthmatic and shift operators
for STD_LOGIC_VECTORs/STD_LOGICs.

I'm confused which library package i should consult, wether to use
STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED. what's the nature of
STD_LOGIC_VECTOR, How it behaves i.e. SIGNED or UNSIGNED??.

Waiting for early response.

--
Thanks in Advance
Vikas Talwar

 

[Neo]

If your requirement dosent operate on signed numbers then go for
unsigned else use signed. std_logic_vector dosent have any numerical
properties so you have to use one of the above to interpret them as
representation of numbers.