Hit Logic

[Vazquez]

Hi,

I have a question concerning a possibility to find out whether
there is a hit or not (cache).

How can I check with few ressources need (Altera Cyclone device)
if there is one or more positions with '1'
within a 32bit-vector (in this case a signal hit='1'
should be the result)?

Thank you very much for your help.


Kind regards
Andrés Vázquez
G&D System Development

 

[Jonathan Bromley]

"Vazquez" <andres.vazquez@gmx.de> wrote in message
news:eee19a7a.0310300536.40db93bb@posting.google.com...

How can I check with few ressources need (Altera Cyclone device)
if there is one or more positions with '1'
within a 32bit-vector (in this case a signal hit='1'
should be the result)?

It should be OK simply to write the obvious VHDL or Verilog:

.....

reg [31:0] hits;
wire hit;
assign hit = (hits != 0);

.....

hit <= '1' when hits = (hits'range => '0') else '0';

.....

Most synthesis tools will make a fair job of
constructing a nice tree of OR gates from this code,
or else use the carry-chain logic if that can be done.
--
Jonathan Bromley, Consultant

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