At that speed you could massively parallel memory chips and read them
out round robin with fast low voltage logic. That would be the 'Rolls
Royce' solution, meaning expensive. We used to do that with power-hungry
ECL but nowadays TI has logic that is much more economical. Or you could
crack out the old math books and do an approximation which boils the
whole thing down to coarser timing within the reach of regular fast
memory chips, plus analog adders (may be doable with plain old resistors
and transistors into a current node) followed by a lowpass. The number
of coefficients and thus the number of bits will depend on how accurate
you require the sinc to be.
If it's image processing do a web search for 'cubic filter'.
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