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It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL files.
I would like to know if anyone has used High-level synthesis recetnly for *real* work and if so, would they recommend that people learn it?
It's been about 3 years since I've done any *serious* FPGA work. I used
mostly VHDL or sometimes my own Matlab scripts to create automated VHDL
files.
I would like to know if anyone has used High-level synthesis recetnly for
*real* work and if so, would they recommend that people learn it?
It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL files.
I would like to know if anyone has used High-level synthesis recetnly for *real* work and if so, would they recommend that people learn it?
It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL files.
I would like to know if anyone has used High-level synthesis recetnly for *real* work and if so, would they recommend that people learn it?
I use the register header file as input to a Python program to generate
the register in VHDL. The Python program will generate a package
containing the register with a std_logic_vector, and functions which
will convert to and from a "record" so I can use the high level view
of the register in VHDL.
Benjamin Couillard <benjamin.couillard@gmail.com> wrote:
It's been about 3 years since I've done any *serious* FPGA work. I used
mostly VHDL or sometimes my own Matlab scripts to create automated VHDL
files.
I would like to know if anyone has used High-level synthesis recetnly for
*real* work and if so, would they recommend that people learn it?
I think it depends a lot on your application area.
If what you do is DSP-style compute, you might be able to use HLS. It might
save writing some VHDL, although if you're good at writing VHDL there might
not be much in it.
If your problem doesn't look much like DSP, I think it'll be more difficult
to bend HLS to your will.
Theo
(my problems rarely look like DSP, so I don't use it)
Den 2019-03-21 kl. 19:40, skrev Benjamin Couillard:
It's been about 3 years since I've done any *serious* FPGA work. I
used mostly VHDL or sometimes my own Matlab scripts to create
automated VHDL files.
I would like to know if anyone has used High-level synthesis recetnly
for *real* work and if so, would they recommend that people learn it?
We are working on a system where we connect an FPGA and a CPU.
The FPGA will implement almost 20-30 peripherals.
The CPU will run Linux, and will need a driver for each type
of peripheral.
The Linux driver for each peripheral type will contain a main header
file, and a file describing the user interface (I.E: the peripheral
registers)
A register could look like:
typedef struct uart_mode_s {
   uint32_t   bits:4;
   uint32_t   parity:1;
   uint32_t   odd:1;
   uint32_t   encoding:2;
   uint32_t   baud:24;
} uart_mode_t;
I use the register header file as input to a Python program to generate
the register in VHDL. The Python program will generate a package
containing the register with a std_logic_vector, and functions which
will convert to and from a "record" so I can use the high level view
of the register in VHDL.
If I change the C header file in the driver, then the VHDL code will
also change, due to dependencies in the build.
Plan to have another Python program which will take a CSV
file and use the contents to instantiate peripherals, and
to generate the interface to the processor, including the address
decoding. (Perhaps a JSON file will be better, though)
This allows me to adopt to changing requirements and save a lot of time
as well as keeping the driver and the peripheral in sync.
I know others that do it the same way.
AP
If you haven't gotten too deep into writing your own code yet, you may
want to check out a project I've been working on sporadically for a
while now. https://github.com/NJDFan/register-maps
There's also a more standard format for describing registers, IP-XACT,
which like mine is XML-based. I found it impossibly obtuse to work
with, but note it for the record.
In article <q731fb$lbr$1@dont-email.me>,
Rob Gaddi <rgaddi@highlandtechnology.invalid> wrote:
If you haven't gotten too deep into writing your own code yet, you may
want to check out a project I've been working on sporadically for a
while now. https://github.com/NJDFan/register-maps
There's also a more standard format for describing registers, IP-XACT,
which like mine is XML-based. I found it impossibly obtuse to work
with, but note it for the record.
IP-XACT is a solution looking for a problem. It's actually quite
horrible, and a bad idea. From the camp of people who think "XML solves
everything, more XML must be better..."
Regarding the register-maps and autogeneration of RTL code, etc.
We did that 10 years ago or so - but moved on to doing the opposite.
We encode all the register information - offsets, masks, bit-field
definitions, descriptions, etc directly in our code - NOT META COMMENTS -
but SystemVerilog RTL code itself. We have catalog logic that checks
for validity (overlaps, etc...), and other rules. A quick simulation
job is run to generate (all sourced from the RTL)
1. Documentation (various formats - txt files, .csv)
2. Header files (*.h, .json, etc..)
3. other meta-data
There's also simulation hooks included to look up address by name, etc,
that ties right into the testbench setup.
Works a charm. Machine generate RTL code always was ugly. Meta
comment parsing was futzy. Now, it's the best of both worlds.
Regards,
Mark
On 3/21/19 9:37 PM, A.P.Richelieu wrote:
Den 2019-03-21 kl. 19:40, skrev Benjamin Couillard:
It's been about 3 years since I've done any *serious* FPGA work. I
used mostly VHDL or sometimes my own Matlab scripts to create
automated VHDL files.
I would like to know if anyone has used High-level synthesis recetnly
for *real* work and if so, would they recommend that people learn it?
We are working on a system where we connect an FPGA and a CPU.
The FPGA will implement almost 20-30 peripherals.
The CPU will run Linux, and will need a driver for each type
of peripheral.
The Linux driver for each peripheral type will contain a main header
file, and a file describing the user interface (I.E: the peripheral
registers)
A register could look like:
typedef struct uart_mode_s {
    uint32_t   bits:4;
    uint32_t   parity:1;
    uint32_t   odd:1;
    uint32_t   encoding:2;
    uint32_t   baud:24;
} uart_mode_t;
I use the register header file as input to a Python program to
generate the register in VHDL. The Python program will generate a package
containing the register with a std_logic_vector, and functions which
will convert to and from a "record" so I can use the high level view
of the register in VHDL.
If I change the C header file in the driver, then the VHDL code will
also change, due to dependencies in the build.
Plan to have another Python program which will take a CSV
file and use the contents to instantiate peripherals, and
to generate the interface to the processor, including the address
decoding. (Perhaps a JSON file will be better, though)
This allows me to adopt to changing requirements and save a lot of time
as well as keeping the driver and the peripheral in sync.
I know others that do it the same way.
AP
If you haven't gotten too deep into writing your own code yet, you may
want to check out a project I've been working on sporadically for a
while now. https://github.com/NJDFan/register-maps
There's also a more standard format for describing registers, IP-XACT,
which like mine is XML-based. I found it impossibly obtuse to work
with, but note it for the record.
Den 2019-03-22 kl. 17:11, skrev Rob Gaddi:
On 3/21/19 9:37 PM, A.P.Richelieu wrote:
Den 2019-03-21 kl. 19:40, skrev Benjamin Couillard:
It's been about 3 years since I've done any *serious* FPGA work. I
used mostly VHDL or sometimes my own Matlab scripts to create
automated VHDL files.
I would like to know if anyone has used High-level synthesis
recetnly for *real* work and if so, would they recommend that people
learn it?
We are working on a system where we connect an FPGA and a CPU.
The FPGA will implement almost 20-30 peripherals.
The CPU will run Linux, and will need a driver for each type
of peripheral.
The Linux driver for each peripheral type will contain a main header
file, and a file describing the user interface (I.E: the peripheral
registers)
A register could look like:
typedef struct uart_mode_s {
    uint32_t   bits:4;
    uint32_t   parity:1;
    uint32_t   odd:1;
    uint32_t   encoding:2;
    uint32_t   baud:24;
} uart_mode_t;
I use the register header file as input to a Python program to
generate the register in VHDL. The Python program will generate a
package
containing the register with a std_logic_vector, and functions which
will convert to and from a "record" so I can use the high level view
of the register in VHDL.
If I change the C header file in the driver, then the VHDL code will
also change, due to dependencies in the build.
Plan to have another Python program which will take a CSV
file and use the contents to instantiate peripherals, and
to generate the interface to the processor, including the address
decoding. (Perhaps a JSON file will be better, though)
This allows me to adopt to changing requirements and save a lot of time
as well as keeping the driver and the peripheral in sync.
I know others that do it the same way.
AP
If you haven't gotten too deep into writing your own code yet, you may
want to check out a project I've been working on sporadically for a
while now. https://github.com/NJDFan/register-maps
There's also a more standard format for describing registers, IP-XACT,
which like mine is XML-based. I found it impossibly obtuse to work
with, but note it for the record.
Thank You,
I will have a look.
I was discussing this with the guy that has generated the FPGA
code for my current project, and he suggested an XML based
approach instead of C.
If I was going that route, to start from a description and
generate both C and VHDL, I would probably use a JSON format,
since they are so much easier to read.
In my mind the best way is to start off with the C driver.
If you like us are running Linux & U-Boot, then you
have an API for the driver, which needs to be followed.
The H/W implementation of all the peripherals I have seen basically
suck, and the C driver implementer has to overcome all the deficiencies
forced upon him/her by the chip designers.
The proper approach is to start with the API and then
figure out how to implement this in a driver in the most efficient way.
spi_xfer(peripheral SPI, uint8_t src, size_t size, enum spi_flags flags)
{
  SPI->START = flags;       // Activate CS on request
  strncpy(SPI->FIFO, src, size);
  SPI->STOP = flags;       // Deactivate CS on request
}
Once I have the driver figured out, I already have the headers,
so I do not want to create XML to regenerate what I already have.
AP
On Sat, 23 Mar 2019 19:45:06 -0700 (PDT)
Kevin Neilson wrote:
"Hardware Construction Language": that's a good phrase. I write a lot of Matlab that generates Verilog. I wish I didn't have to, but that's the way it is.
Could you construct and simulate with MyHDL? The verilog
would then be just a simple export. [1]
Jan Coombs
On Sunday, March 24, 2019 at 8:31:34 AM UTC+1, Jan Coombs wrote:
On Sat, 23 Mar 2019 19:45:06 -0700 (PDT)
Kevin Neilson wrote:
"Hardware Construction Language": that's a good phrase. I write a lot of Matlab that generates Verilog. I wish I didn't have to, but that's the way it is.
Could you construct and simulate with MyHDL? The verilog
would then be just a simple export. [1]
Jan Coombs
I read on the myhdl discourse that there seems to be a problem with the myhdl owner not maintaining myhdl the way a proper project owner should. Care to comment on that?
--
Svenn
On Sun, 24 Mar 2019 08:46:20 -0700 (PDT)
Svenn Are Bjerkem wrote:
On Sunday, March 24, 2019 at 8:31:34 AM UTC+1, Jan Coombs wrote:
On Sat, 23 Mar 2019 19:45:06 -0700 (PDT)
Kevin Neilson wrote:
"Hardware Construction Language": that's a good phrase. I write a lot of Matlab that generates Verilog. I wish I didn't have to, but that's the way it is.
Could you construct and simulate with MyHDL? The verilog
would then be just a simple export. [1]
Jan Coombs
I read on the myhdl discourse that there seems to be a problem with the myhdl owner not maintaining myhdl the way a proper project owner should. Care to comment on that?
Yes, this is a problem. The BDFL found time to consolidate
progress to a 0.10 release. The team look capable, but their
interests will likely diverge/fork if the leadership does not
improve.
What else combines the constructional power of the Python
ecosystem, with simulation speed equal to other free tools
[1], and spits out Verilog or VHDL?
Den 2019-03-23 kl. 05:43, skrev A.P.Richelieu:
Den 2019-03-22 kl. 17:11, skrev Rob Gaddi:
On 3/21/19 9:37 PM, A.P.Richelieu wrote:
Den 2019-03-21 kl. 19:40, skrev Benjamin Couillard:
It's been about 3 years since I've done any *serious* FPGA work. I
used mostly VHDL or sometimes my own Matlab scripts to create
automated VHDL files.
I would like to know if anyone has used High-level synthesis
recetnly for *real* work and if so, would they recommend that
people learn it?
We are working on a system where we connect an FPGA and a CPU.
The FPGA will implement almost 20-30 peripherals.
The CPU will run Linux, and will need a driver for each type
of peripheral.
The Linux driver for each peripheral type will contain a main header
file, and a file describing the user interface (I.E: the peripheral
registers)
A register could look like:
typedef struct uart_mode_s {
    uint32_t   bits:4;
    uint32_t   parity:1;
    uint32_t   odd:1;
    uint32_t   encoding:2;
    uint32_t   baud:24;
} uart_mode_t;
I use the register header file as input to a Python program to
generate the register in VHDL. The Python program will generate a
package
containing the register with a std_logic_vector, and functions which
will convert to and from a "record" so I can use the high level view
of the register in VHDL.
If I change the C header file in the driver, then the VHDL code will
also change, due to dependencies in the build.
Plan to have another Python program which will take a CSV
file and use the contents to instantiate peripherals, and
to generate the interface to the processor, including the address
decoding. (Perhaps a JSON file will be better, though)
This allows me to adopt to changing requirements and save a lot of time
as well as keeping the driver and the peripheral in sync.
I know others that do it the same way.
AP
If you haven't gotten too deep into writing your own code yet, you
may want to check out a project I've been working on sporadically for
a while now. https://github.com/NJDFan/register-maps
There's also a more standard format for describing registers,
IP-XACT, which like mine is XML-based. I found it impossibly obtuse
to work with, but note it for the record.
Thank You,
I will have a look.
I was discussing this with the guy that has generated the FPGA
code for my current project, and he suggested an XML based
approach instead of C.
If I was going that route, to start from a description and
generate both C and VHDL, I would probably use a JSON format,
since they are so much easier to read.
In my mind the best way is to start off with the C driver.
If you like us are running Linux & U-Boot, then you
have an API for the driver, which needs to be followed.
The H/W implementation of all the peripherals I have seen basically
suck, and the C driver implementer has to overcome all the deficiencies
forced upon him/her by the chip designers.
The proper approach is to start with the API and then
figure out how to implement this in a driver in the most efficient way.
spi_xfer(peripheral SPI, uint8_t src, size_t size, enum spi_flags flags)
{
   SPI->START = flags;       // Activate CS on request
   strncpy(SPI->FIFO, src, size);
   SPI->STOP = flags;       // Deactivate CS on request
}
Once I have the driver figured out, I already have the headers,
so I do not want to create XML to regenerate what I already have.
AP
Had a brief look at your stuff at
* https://github.com/NJDFan/register-maps
This is mainly to do address decoding, right?
Do you have any support for the actual fields inside the registers?
That is a primary function I would be looking for.
I can actually see the use of such tool for me,
if my C struct parser generates the XML (or JSON)
for an intermediate representation.
BR
AP