High-activity bit sequence wanted

Hi,
I have to test a bit of hardware that I have designed in VHDL and for
part of it, I would like
to inject an N-bit 'high activity' sequence of values.

If I wanted a low activity bit sequence then I would choose a Gray Code
counter to generate the sequence, as only one bit changes between
successive values.
What I am after is an easy to generate sequence in which a large number
of bits change between successive values N-1 bit changes would be
great!.

I have tried to google for an answer, but I don't know what to google
for.

Thanks in advance, Paddy.

 

paddy3118@netscape.net wrote:

Hi,
I have to test a bit of hardware that I have designed in VHDL and for
part of it, I would like
to inject an N-bit 'high activity' sequence of values.

If I wanted a low activity bit sequence then I would choose a Gray Code
counter to generate the sequence, as only one bit changes between
successive values.
What I am after is an easy to generate sequence in which a large number
of bits change between successive values N-1 bit changes would be
great!.

I have tried to google for an answer, but I don't know what to google
for.

How about a Gray Code, but invert all the bits every second word? That
would give you N-1 bits changing every clock.

Regards,
Allan

 

Thanks Allan,
That is indeed what I was after.

http://groups.google.com/group/sci.math/browse_frm/thread/c9862c44b4db7c85/1d23b0bebea4d4e4#1d23b0bebea4d4e4

- Paddy.

 

-- START counters.vhd

--
-- TestBench Counters
--
-- Author: Paddy McCarthy
-- Paddy3118@netscape.net
--
-- Copyright (C) 2005 Donald `Paddy` mcCarthy
-- Use and abuse this source as you will but keep this notice.
-- This file is good for me. You use it at your own risk.
--


--
-- N bit counter, Gray code counter, and High entropy counter.
-- Whereas the Gray code counter minimises the bits changing between
counts
-- The High Entropy count maximises the bits changing on each count.
--

Library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

Library work;
use work.all;


entity counters is
generic (
bits : in integer := 4 -- bits in counters
);

port (
signal clk : in std_logic ;
signal reset_n : in std_logic ;
signal count, gray, hi_entropy : out std_logic_vector( bits-1 downto
0 )
);

end entity counters ;


architecture RTL of counters is
begin

counter : process (reset_n, clk)
variable cnt, g : unsigned(bits-1 downto 0);

begin
if reset_n = '0' then
cnt := (others => '0');
count <= (others => '0');
gray <= (others => '0');
hi_entropy <= (others => '0');
elsif clk'event and clk = '1' then
cnt := cnt + 1;
g := cnt xor shift_right(cnt, 1);
count <= std_logic_vector(cnt);
gray <= std_logic_vector(g);
if cnt(0) = '0' then
hi_entropy <= std_logic_vector(g);
else
hi_entropy <= std_logic_vector( not (g));
end if;
end if;
end process;


end RTL;


-- END counters.vhd --