hierarchy

[Brannon King]

I have a 1.5 MB file of extremely hierarchical Verilog. It brings XST to its
knees with a lame message about 2GB of RAM already in use.

Who makes the best Verilog compiler?
Who can handle hierarchical files that big?
Who flattens before they attempt to compile?
Is there a structural flattener for Windows anywhere?
Is there an EDIF flattener anywhere?
Would VHDL be a better choice in this case?

 

[Abhijit]

Hi Branon,

Can you provide more info regarding what exactly you want to do?
What do you mean by a compiler? A parser, a simulator or some other
tool?

Even you use a structural flattener/Vhdl the design will remain big
and will not solve the problem of current tools.

Abhijit

"Brannon King" <bking@starbridgesystems.com> wrote in message news:<bf9ohc$bd9@dispatch.concentric.net>...

I have a 1.5 MB file of extremely hierarchical Verilog. It brings XST to its
knees with a lame message about 2GB of RAM already in use.

Who makes the best Verilog compiler?
Who can handle hierarchical files that big?
Who flattens before they attempt to compile?
Is there a structural flattener for Windows anywhere?
Is there an EDIF flattener anywhere?
Would VHDL be a better choice in this case?

 

[Andrew Paule]

Brannon -

the XST from the part manufacturer (you know who it is) is a good
compiler for smaller projects, but later versions of the software
contain another compiler that may be more appropriate. One of the
problems that you are facing is a tool supplied by a particular vendor,
that has been designed with different needs than yours. There are
several very good verilog/vhdl compilers out there, but how fast can you
afford to go - if what you have will not go fast enough, then you should
look into tools that are not device specific, and maybe break the file
up into smaller modules that can be indiviually compiled and then mapped
into a device after the EDIFs have been generated individually.

Andrew Paule

Brannon King wrote:

I have a 1.5 MB file of extremely hierarchical Verilog. It brings XST to its
knees with a lame message about 2GB of RAM already in use.

Who makes the best Verilog compiler?
Who can handle hierarchical files that big?
Who flattens before they attempt to compile?
Is there a structural flattener for Windows anywhere?
Is there an EDIF flattener anywhere?
Would VHDL be a better choice in this case?

 

[Brannon King]

I have a 1.5 MB file containing 3500 unique modules. I want to map that to a
Xilinx xc2v6000-4ff1152 chip. Both Synplify Pro and Xilinx XST run out of
memory while attempting to do that.


"Abhijit" <chakrabarty@hotmail.com> wrote in message
news:f42ec3b1.0307182303.51ad660f@posting.google.com...

Hi Branon,

Can you provide more info regarding what exactly you want to do?
What do you mean by a compiler? A parser, a simulator or some other
tool?

Even you use a structural flattener/Vhdl the design will remain big
and will not solve the problem of current tools.

Abhijit

"Brannon King" <bking@starbridgesystems.com> wrote in message
news:<bf9ohc$bd9@dispatch.concentric.net>...
I have a 1.5 MB file of extremely hierarchical Verilog. It brings XST to
its
knees with a lame message about 2GB of RAM already in use.

Who makes the best Verilog compiler?
Who can handle hierarchical files that big?
Who flattens before they attempt to compile?
Is there a structural flattener for Windows anywhere?
Is there an EDIF flattener anywhere?
Would VHDL be a better choice in this case?

 

[Andrew Paule]

Brannon:

try this (use synplify pro - I know it better than XST) -

you first have to break up the file into some smaller ones containing
only a few modules - maybe some of your base modules would be a good
start (lowest level).

make a new project, add some of the files and the lib for the chip -
compile to a mapped verilog netlist.

repeat as many times as necessary -

make a final project
take the highest level file and the resultant mapped verilog netlists
(these won't get recompiled - sort of like the don't touch directive)
and see if this will compile - it should

Andrew


Brannon King wrote:

I have a 1.5 MB file containing 3500 unique modules. I want to map that to a
Xilinx xc2v6000-4ff1152 chip. Both Synplify Pro and Xilinx XST run out of
memory while attempting to do that.


"Abhijit" <chakrabarty@hotmail.com> wrote in message
news:f42ec3b1.0307182303.51ad660f@posting.google.com...


Hi Branon,

Can you provide more info regarding what exactly you want to do?
What do you mean by a compiler? A parser, a simulator or some other
tool?

Even you use a structural flattener/Vhdl the design will remain big
and will not solve the problem of current tools.

Abhijit

"Brannon King" <bking@starbridgesystems.com> wrote in message


news:<bf9ohc$bd9@dispatch.concentric.net>...


I have a 1.5 MB file of extremely hierarchical Verilog. It brings XST to


its


knees with a lame message about 2GB of RAM already in use.

Who makes the best Verilog compiler?
Who can handle hierarchical files that big?
Who flattens before they attempt to compile?
Is there a structural flattener for Windows anywhere?
Is there an EDIF flattener anywhere?
Would VHDL be a better choice in this case?