hierarchical signal names inside generate statements

[Peter Riocreux]

What follows seems to be true in Modelsim v5.8b and 5.8c, but I cannot
speak for other tools or other Modelsim versions.

With the code at the end of this post, if the instantiation of X is
replaced by that of (the commented-out) Y or Z then the andtree module
works as expected, but with X as the instantiation, the inputs to the
gates thus generated are not driven so we get an x output when all
input bits are 1.

In the LRM, there are no examples that I could find of using a
hierarchical name on a port of an instantiation inside a generate, so
I can't tell if everything is as everyone else would expect, or if one
or both of the working variants should not, or if the one not working
should, or if I have made some kind of error.

Can anyone enlighten me as to whether this is expected behaviour, my
error or the tool's error.


Peter


----8<--------8<--------8<--------8<--------8<--------8<----
`timescale 1ns/10ps

module my_and2(o, i0, i1);
output o;
input i0, i1;
and I0 (o, i0, i1);
endmodule

module andtree (o, a);
parameter SIZE = 8;
output o;
input [SIZE-1:0] a;

genvar i, j;
generate
for (j=(SIZE/2); j>=0; j=j-1) begin:LEVEL
for(i=0; i<(2**j); i=i+1) begin:GATE
if (j<(SIZE/2))
begin
assign p1 = LEVEL[j+1].GATE[i*2].t1;
assign p2 = LEVEL[j+1].GATE[i*2+1].t1;
my_and2 X (t1, LEVEL[j+1].GATE[i*2].t1, LEVEL[j+1].GATE[i*2+1].t1);
//my_and2 Y (t1, p1, p2);
//and Z (t1, LEVEL[j+1].GATE[i*2].t1, LEVEL[j+1].GATE[i*2+1].t1);
end
else
begin
buf B( t1, a);
end
end
end
endgenerate
assign o = LEVEL[0].GATE[0].t1;

endmodule

module test;
reg [3:0] a;
wire o;

andtree #(4) I0 (o, a);

initial $monitor($time,, "a=", a, " o=", o);

initial begin
a = 0;
#10 a = 1;
#10 a = 4'hf;
#10 $finish;
end
endmodule
----8<--------8<--------8<--------8<--------8<--------8<----

 

[Just an Illusion]

Hi Peter,

I'm not sure that can solve your problem, but you seems having forget
some thing about 'generate'

The 'generate' give you the capability to regroup some part of code with
similar syntax.

But the code must remain valid when you made 'manual' deployment of loops.

In your case, you instantiate (size/2 * 2^size/2 = 4 * 16 =) 64 times
the component my_and2 X.

I am not sure that you haven't instantiation problem after ;-)
I think that you must add something to differentiate all implementations.

If I made a intrepretation mistake, I will be happy to learn.

JaI

Peter Riocreux wrote:

snip


----8<--------8<--------8<--------8<--------8<--------8<----
`timescale 1ns/10ps

module my_and2(o, i0, i1);
output o;
input i0, i1;
and I0 (o, i0, i1);
endmodule

module andtree (o, a);
parameter SIZE = 8;
output o;
input [SIZE-1:0] a;

genvar i, j;
generate
for (j=(SIZE/2); j>=0; j=j-1) begin:LEVEL
for(i=0; i<(2**j); i=i+1) begin:GATE
if (j<(SIZE/2))
begin
assign p1 = LEVEL[j+1].GATE[i*2].t1;
assign p2 = LEVEL[j+1].GATE[i*2+1].t1;
my_and2 X (t1, LEVEL[j+1].GATE[i*2].t1, LEVEL[j+1].GATE[i*2+1].t1);
//my_and2 Y (t1, p1, p2);
//and Z (t1, LEVEL[j+1].GATE[i*2].t1, LEVEL[j+1].GATE[i*2+1].t1);
end
else
begin
buf B( t1, a);
end
end
end
endgenerate
assign o = LEVEL[0].GATE[0].t1;

endmodule

module test;
reg [3:0] a;
wire o;

andtree #(4) I0 (o, a);

initial $monitor($time,, "a=", a, " o=", o);

initial begin
a = 0;
#10 a = 1;
#10 a = 4'hf;
#10 $finish;
end
endmodule
----8<--------8<--------8<--------8<--------8<--------8<----