H
hssig
Guest
Hi newsgroup,
I am trying to use VHDL-2008 Hierarchical References in the following way:
process(all)
begin
for k in 0 to 15 loop
tap_vec(k) <= << signal .tb.uut.g_GenArr(k).i_rx.tap_sig : std_logic >>;
end loop;
end process;
"g_GenArr" contains 16 components instantiated in a generate loop.
When compiling with Modelsim 10.1c I get the following error message:
(vcom-1303) An index in an external name must be a globally static expression.
How can I solve that problem?
Cheers, hssig
I am trying to use VHDL-2008 Hierarchical References in the following way:
process(all)
begin
for k in 0 to 15 loop
tap_vec(k) <= << signal .tb.uut.g_GenArr(k).i_rx.tap_sig : std_logic >>;
end loop;
end process;
"g_GenArr" contains 16 components instantiated in a generate loop.
When compiling with Modelsim 10.1c I get the following error message:
(vcom-1303) An index in an external name must be a globally static expression.
How can I solve that problem?
Cheers, hssig