Hierarchical names as parameters

[Neo]

I want to pass hierarchical paths as defparams to modules, is this
possible in verilog/SV?

 

[Jonathan Bromley]

On Dec 10, 6:09 am, Neo <zingafri...@yahoo.com> wrote:

I want to pass hierarchical paths as defparams to modules,
is this possible in verilog

No. A parameter is simply a value; it can't be a reference
to some other thing in the instance hierarchy.

SV?

In a way, yes - but not with a parameter. You could use a
virtual interface variable, and fill in that variable's value
with the hierarchical path name of an interface that you
want to access.

Maybe closer to the spirit of your question, you can also
link a module's port of interface type to a specific interface
instance.

Perhaps you could describe the real point of your question:
what are you actually trying to achieve?
--
Jonathan Bromley

 

[Neo]

On Dec 10, 1:36 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Dec 10, 6:09 am, Neo <zingafri...@yahoo.com> wrote:

I want to pass hierarchical paths as defparams to modules,
is this possible in verilog

No.  A parameter is simply a value; it can't be a reference
to some other thing in the instance hierarchy.

SV?

In a way, yes - but not with a parameter.  You could use a
virtual interface variable, and fill in that variable's value
with the hierarchical path name of an interface that you
want to access.

Maybe closer to the spirit of your question, you can also
link a module's port of interface type to a specific interface
instance.

Perhaps you could describe the real point of your question:
what are you actually trying to achieve?
--
Jonathan Bromley

Thanks Jonathan,
What I want is: access the interface of modules for my monitor and
this monitor can be instantiated multiple times with hooks to
different modules.
An interface is probably the way to go but if there was some other
simpler way it would have been nice. Like values if we could pass
paths in parameters it would be so easy. And of course these have to
be synthesizeable.

 

[Jonathan Bromley]

On Dec 10, 10:34 am, Neo <zingafri...@yahoo.com> wrote:

What I want is: access the interface of modules for my monitor and
this monitor can be instantiated multiple times with hooks to
different modules.
An interface is probably the way to go

Right. Interfaces were designed to solve exactly this problem.

You could try my DVCon'07 paper on designing with interfaces:
http://www.doulos.com/knowhow/sysverilog/DVCon07/DVCon07_SysVlog.php
or look at the Sutherland/Davidmann/Flake book on SV design.

And of course these have to be synthesizeable.

Synthesis of interfaces is now fine in most tools (no support
in Xilinx XST yet, as far as I know, but others are OK).
When using interfaces for synthesizable design, remember
ALWAYS to use modports for the connections - some synth tools
don't support connection to interfaces without modports.
--
Jonathan Bromley

 

[Neo]

On Dec 10, 3:03 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Dec 10, 10:34 am, Neo <zingafri...@yahoo.com> wrote:

What I want is: access the interface of modules for my monitor and
this monitor can be instantiated multiple times with hooks to
different modules.
An interface is probably the way to go

Right.  Interfaces were designed to solve exactly this problem.

You could try my DVCon'07 paper on designing with interfaces:
 http://www.doulos.com/knowhow/sysverilog/DVCon07/DVCon07_SysVlog.php
or look at the Sutherland/Davidmann/Flake book on SV design.

And of course these have to be synthesizeable.

Synthesis of interfaces is now fine in most tools (no support
in Xilinx XST yet, as far as I know, but others are OK).
When using interfaces for synthesizable design, remember
ALWAYS to use modports for the connections - some synth tools
don't support connection to interfaces without modports.
--
Jonathan Bromley

Thanks again.