Hiding of subprogram designators

[David Jones]

From VHDL-93 LRM section 10.3, page 144, lines 143-144:

Within the specification of a subprogram, every declaration with the same
designator as the subprogram is hidden. Where hidden in this manner, a
declaration is visible neither by selection nor directly.

Read one way, a subprogram declaration has the same designator as itself,
therefore it should be hidden within the specification of the subprogram.
As a consequence, it should not be possible to call a subprogram recursively.

Casual experimentation with VHDL Simili indicates that this is not so (i.e.
recursion is possible) and I would be surprised if recursion were not possible.

If I try to overload a subprogram name as a signal, then I'm creating a
homograph, and we already have rules to deal with that. If I try to overload
a subprogram name as another subprogram, that works, and one overloaded
subprogram can even call the other!

Can someone clarify exactly what the spec is trying to prevent and why?

 

[Alan Fitch]

"David Jones" <dej@coup.inode.org> wrote in message
news:XMbub.7149$iT4.623310@news20.bellglobal.com...

From VHDL-93 LRM section 10.3, page 144, lines 143-144:

Within the specification of a subprogram, every declaration with
the same
designator as the subprogram is hidden. Where hidden in this
manner, a
declaration is visible neither by selection nor directly.

Read one way, a subprogram declaration has the same designator as
itself,
therefore it should be hidden within the specification of the
subprogram.
As a consequence, it should not be possible to call a subprogram
recursively.

Casual experimentation with VHDL Simili indicates that this is not
so (i.e.
recursion is possible) and I would be surprised if recursion were
not possible.

If I try to overload a subprogram name as a signal, then I'm
creating a
homograph, and we already have rules to deal with that. If I try to
overload
a subprogram name as another subprogram, that works, and one
overloaded
subprogram can even call the other!

Can someone clarify exactly what the spec is trying to prevent and
why?

Hi David, as usual with the LRM you have to look up every phrase
very carefully. The words "subprogram specification" refer to the
the part of the subprogram from the start of it to the ';' or the 'is'
i.e.

procedure fred (variable A : in std_logic) ;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
subprogram specification

or

impure function blob (constant A : BOOLEAN) return integer is
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
variable I : INTEGER;
begin
-- do something impure!

return I

end function;

In other words, all it's saying is that you can't have a parameter
with
the same name as the subprogram, e.g.

procedure fred (variable fred : in std_logic) is


Have a look at section at the syntax summary in Annex A, p221, for
a summary of what a subprogram specification is, or look in chapter
2

kind regards

Alan

P.S. There's no problem with recursion. In fact because declaration
and body can be separated, it's possible to write mutually recursive
procedures if you want to!

--
Alan Fitch
Consultant

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