hex notation

[Andreas H?lscher]

Hi,
I have code like this:

cs_reg <= '1' when Adr = conv_std_logic_vector(21,8) else '0';

To get my code more readable I want to use hexadecimal numbers for the
address. I tried to replace the 21 with 0x15, 15h, x"15" but nothing
works.

Any hint?

Thanks,
Andreas

 

[Matt North]

"Andreas H?lscher" <ah@dsa-ac.de> wrote in message
news:6c023d19.0312100338.3c345bd2@posting.google.com...

Hi,
I have code like this:

cs_reg <= '1' when Adr = conv_std_logic_vector(21,8) else '0';

To get my code more readable I want to use hexadecimal numbers for the
address. I tried to replace the 21 with 0x15, 15h, x"15" but nothing
works.

Any hint?

Thanks,
Andreas

X"15" does work but the target type has to be of bit_vector.

------------------------------------
signal Adr: bit_vector(7 downto 0);

cs_reg<='1' when Adr=X"15" else '0';
------------------------------------

The conversion function to_bitvector is found in the package std_logic_1164
and converts type std_logic_vector and std_ulogic_vector.

Matt

 

[Egbert Molenkamp]

X"15" does work but the target type has to be of bit_vector.

------------------------------------
signal Adr: bit_vector(7 downto 0);

cs_reg<='1' when Adr=X"15" else '0';
------------------------------------
In VHDL'87 "Adr" should be a bit_vector.

Since VHDL-1993 this is replaced such that it is only required that an
element of the vector at least contains the character literals '0' and '1'.
So bit_vector is still valid, but also std_logic_vector, std_ulogic_vector,
unsigned,...

Egbert Molenkamp