P
Pratip Mukherjee
Guest
Hi,
If I have a port defined as std_logic_vector(n downto 0), Quartus simulator
is showing the individual bits in binary values. How do I make it display
all the bits together in a hex mode.
Thanks in advance.
Pratip Mukherjee
If I have a port defined as std_logic_vector(n downto 0), Quartus simulator
is showing the individual bits in binary values. How do I make it display
all the bits together in a hex mode.
Thanks in advance.
Pratip Mukherjee