Hercules LVS

[Sabyasachi]

Hi everybody ,

I am trying to check LVS in hercules. I have checked my layout in
assura and generated gds from it. I have generated netlist by analog
environment --- > simulation -----> creat netlist .

while running hercules i am getting the following error.


Reading "/mtech/sabyasachi/cmos9/ESD_ring19_netlist" netlist ...
Skipping unsupported statement "//".
Skipping unsupported statement "//".
Skipping unsupported statement "//".
Skipping unsupported statement "subckt".
Skipping unsupported statement "snc".
Skipping unsupported statement "snc".
Creating Top Block "NT_TOP_ESD_ring19_netlist"
=FATAL: parse error at or near line 14 in "/mtech/sabyasachi/cmos9/
ESD_ring19_netlist" near token : "
"
Hercules Run: Time= 0:00:00 User=0.10 System=0.01
Hercules is done.


please help to fix this problem

cheers
Sabyasachi

 

[Marc Heise]

Am 24.03.2010 11:20, schrieb Sabyasachi:

Hi everybody ,

I am trying to check LVS in hercules. I have checked my layout in
assura and generated gds from it. I have generated netlist by analog
environment ---> simulation -----> creat netlist .

while running hercules i am getting the following error.


Reading "/mtech/sabyasachi/cmos9/ESD_ring19_netlist" netlist ...
Skipping unsupported statement "//".
Skipping unsupported statement "//".
Skipping unsupported statement "//".
Skipping unsupported statement "subckt".
Skipping unsupported statement "snc".
Skipping unsupported statement "snc".
Creating Top Block "NT_TOP_ESD_ring19_netlist"
=FATAL: parse error at or near line 14 in "/mtech/sabyasachi/cmos9/
ESD_ring19_netlist" near token : "
"
Hercules Run: Time= 0:00:00 User=0.10 System=0.01
Hercules is done.


please help to fix this problem

cheers
Sabyasachi

Hercules isn't a Cadence tool, so I only can guess here
since I have no practical experience nor do I have access to
the documentation.
I think that a simulation netlist is not the right format to use
with a LVS tool. Please check your manual about how the schematic
netlist should be created and in which format.

Marc

 

[Sabyasachi]

Thank you Marc for your information .

Can anybody help me regarding the schematic file which Marc is talking
of. How to generate this schematic file in cadence on which hercules
LVS will run properly.


Cheers
Sabyasachi

 

On Mar 24, 3:20 am, Sabyasachi <sabyasachi.iit...@gmail.com> wrote:

Hi everybody ,

I am trying to check LVS in hercules. I have checked my layout in
assura and generated gds from it. I have generated netlist by analog
environment --- > simulation -----> creat netlist .

while running hercules i am getting the following error.

Reading "/mtech/sabyasachi/cmos9/ESD_ring19_netlist" netlist ...
Skipping unsupported statement "//".
Skipping unsupported statement "//".
Skipping unsupported statement "//".
Skipping unsupported statement "subckt".

You're giving Hercules a Spectre netlist, you can't do that.
Hercules, Calibre (and Assura, for that matter) do not read
Spectre format, they read Spice and CDL. And you don't
want Spice, you want CDL (trust me).

You'll want to do something like File->Export->CDL from the CIW.
(This is from memory) I think there will be an "analog" option
there, you'll want to select that, probably. You have to have
auCdl (I think that's right) cellviews in your transistor library, and
accompanying CDF simInfo data; if you don't have that, you'll
be out of luck.

Your Assura reference manual has a good CDL format section,
use it.

-Jay-

 

[Sabyasachi]

Thanks Jay,

Now I am giving CDL netlist and my problem is solved. Thanks for your
information.

Cheers
Sabyasachi