Help with Verilog code flow + Code posted.

[dash82]

Hi,

My questions are regarding the code that is posted at the end.

I am a bit confused as to how the flow of the code would proceed.
There is no "always" statement in the code.

First, two instances of cic_interp are instantiated .i.e.
cic_interp_i & cic_interp_q . The signal assignments happen. The most
significant signals i_in and q_in are assigned to signal_in of
cic_interp_i & cic_interp_q.

Question 1:

Do both (cic_interp_i & cic_interp_q) instantiation and assignment
happen at the execution time 0 ?

Or for that matter, all (cic_interp_i , cic_interp_q, phase_acc_tx &
tx_cordic_0) instantiations happen at time 0 ?

I am doubtful of what I am thinking above. Because I can see that
cic_interp_i's output signal bb_i is being assigned as input in
tx_cordic_0. So, if I go by my logic, then wrong assignments would
happen.

Question 2:

Lets assume that some logic is defined for all (cic_interp_i ,
cic_interp_q, phase_acc_tx & tx_cordic_0) modules somewhere else. And
suppose cic_inter_i module logic takes 5 clock cycles to finish its
task and tx_cordic_0 module logic takes 8 clock cycles to finish its
task. So, will tx_cordic_0 wait for 5 clock cycles for cic_interp_i to
finish its task, produce bb_i and then tx_cordic_0 uses this new bb_i
and then takes additional 8 clock cycles to finish its task ?
So, total completion time would be 13 clock cycles ? Am I thinking
right or there is something wrong ?

Thanks !

Shah.


tx_chain.v code (The code is open source and protected by GNU GPL. I
have omitted the license details to save space.)

------------------
module tx_chain
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);

wire [15:0] bb_i, bb_q;

cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(i_in),.signal_out(bb_i) );

cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
.signal_in(q_in),.signal_out(bb_q) );

`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;

phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );

cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif

endmodule // tx_chain

 

[Mike Treseler]

dash82 wrote:

My questions are regarding the code that is posted at the end.
I am a bit confused as to how the flow of the code would proceed.
There is no "always" statement in the code.

That code is a structural description
of how two wire up four module instances.
The always blocks are in the base modules.
That is where the code flows.
Try stepping through a simulation.

-- Mike Treseler

 

[Jonathan Bromley]

On Fri, 30 Nov 2007 13:47:54 -0800 (PST),
dash82 <dhavalrules@gmail.com> wrote:

Mike, you are right. The 'always' statement is defined in the base
classes. And I do understand the flow in those base classes.

Base classes??? This is Verilog, not C++.
Modules are not classes. Module instances are assembled by
the elaboration process, *before* execution of your "initial"
and "always" blocks begins. Module instances are static.

But, somehow I am confused with the flow for this top module.

module stimulus;
reg clock;
reg reset;
reg enable;
reg sample_strobe;
reg interpolator_strobe;
wire [7:0] interp_rate ;
wire [31:0] freq ;
wire [15:0] i_in ;
wire [15:0] q_in ;
wire [15:0] i_out ;
wire [15:0] q_out ;

tx_chain testing (
clock,reset,enable,
interp_rate,sample_strobe,interpolator_strobe,
freq,i_in,q_in,i_out,q_out);

initial
begin
clock = 1'b1;
reset = 1'b0 ;
enable = 1'b1 ;
sample_strobe = 1'b1 ;
interpolator_strobe = 1'b1 ;
end

endmodule

Don't you think it might be a good idea to run the clock for
at least a few cycles, to see what happens? And, maybe,
to reset the system? Right now you merely have an "initial"
block that sets the device's inputs to certain values at
time zero, and then goes to sleep. I don't think
the "tx_chain" device you're trying to test would find
that very stimulating...

Here's a sketch of the way I typically start to write
a really simple Verilog testbench. It's generating totally
randomized input, which probably won't be very useful.
Over to you to decide what you *really* want to do.
But at least you should see some values being pushed
through your design. Once you can see some activity,
it should be fairly easy to start generating useful
and interesting stimulus.

module tb;

// Things that will be inputs to the device under test
// (DUT) are declared as "reg" so I can write to them
reg clock;
reg reset;
reg enable;
reg sample_strobe;
reg interpolator_strobe;
reg [7:0] interp_rate ;
reg [31:0] freq ;
reg [15:0] i_in ;
reg [15:0] q_in ;

// Things that will be outputs from the DUT are wires.
// Observe them with the simulator's waveform viewer.
wire [15:0] i_out ;
wire [15:0] q_out ;

// The device under test
tx_chain testing (....port connections as you had....);

reg stop; // needed to stop simulation running for ever

// Reset generator
initial begin
// Assert reset
reset = 1'b1;
// Wait for two clock cycles...
repeat (2) @(negedge clock);
// then deassert reset
reset = 1'b0;
end

// clock generator
initial begin
stop = 1'b0;
clock = 1'b0;
while (!stop)
#5 clock = ~clock;
end

// stimulus generator
initial begin : stim_gen

int seed;

// Set up seed for random stimulus generator
seed = 42;
// Set up sensible values on control inputs
// (you probably want to choose different values?)
interp_rate = 3;
freq = 20;
// What is the enable for???? I'll just jam it true,
// to see what happens.
enable = 1'b1;

// Now generate some input over the first 100 clocks
repeat (100) @(negedge clock) begin
// Randomly assert strobe signals with 50% probability
sample_strobe = $dist_uniform(seed, 0, 1);
interpolator_strobe = $dist_uniform(seed, 0, 1);
// Random 16-bit values on quadrature inputs
i_in = $dist_uniform(seed, -32768, 32767);
q_in = $dist_uniform(seed, -32768, 32767);
end

// And finally stop:
stop = 1;

end

endmodule

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[dash82]

On Nov 30, 10:03 am, Mike Treseler <mike_trese...@comcast.net> wrote:

dash82 wrote:
My questions are regarding the code that is posted at the end.
I am a bit confused as to how the flow of the code would proceed.
There is no "always" statement in the code.

That code is a structural description
of how two wire up four module instances.
The always blocks are in the base modules.
That is where the code flows.
Try stepping through a simulation.

-- Mike Treseler

Thank you Mike. I tried writing a simple test bench and stepping
through my
code simulation, but it just would'nt work. I am including my code
below. I know the test bench is pretty stupid,
but I atleast expected it to enter my code.

I would be grateful if Mike or anyone else in the group could give a
brief indication as to :

Do both (cic_interp_i & cic_interp_q) instantiation and assignment
happen at the execution time 0 ?

Or for that matter, all (cic_interp_i , cic_interp_q, phase_acc_tx &
tx_cordic_0) instantiations happen at time 0 ? If not, what would be
the flow.

Mike, you are right. The 'always' statement is defined in the base
classes. And I do understand the flow in those base classes.
But, somehow I am confused with the flow for this top module.

Any help is greatly appreciated.

Thanks.


module stimulus;
reg clock;
reg reset;
reg enable;
reg sample_strobe;
reg interpolator_strobe;
wire [7:0] interp_rate ;
wire [31:0] freq ;
wire [15:0] i_in ;
wire [15:0] q_in ;
wire [15:0] i_out ;
wire [15:0] q_out ;

tx_chain testing
(clock,reset,enable,interp_rate,sample_strobe,interpolator_strobe,freq,i_in,q_in,i_out,
q_out);

initial
begin
clock = 1'b1;
reset = 1'b0 ;
enable = 1'b1 ;
sample_strobe = 1'b1 ;
interpolator_strobe = 1'b1 ;

end

endmodule