help with "timeout" scheme in Verilog TB

[SB]

All,

I have a task in a Verilog testbench that waits for the assertion of a
"ready" signal from the DUT.

@(posedge ready_signal) ; //continue with the task flow

In the testbench's present form, if the ready signal should never
assert for a given input condition (which is possible), the testbench
will hang, forever polling the ready signal.

I have tried to develop a timeout scheme that will limit the number of
operating clock cycles that the testbench will wait for the ready
signal, before it abandons the wait and moves on with the stimulus. I
have not been succesful.

I have tried a down-counter scheme in parallel with the line of code
above in a fork-join statement. However, the fork-join will only
finish when both forks are complete, so this will not help me. I can
develop a count-down scheme fine, but in the event that the "end of
the count" is reached, I am unsure how to "skip" the @(posedge) line
above.

Can anybody suggest a scheme that will do this?

Regards
SB

 

[Muzaffer Kal]

On Sat, 22 Aug 2009 14:22:43 -0700 (PDT), SB <paulsheehan81@yahoo.com>
wrote:

All,

I have a task in a Verilog testbench that waits for the assertion of a
"ready" signal from the DUT.

@(posedge ready_signal) ; //continue with the task flow

In the testbench's present form, if the ready signal should never
assert for a given input condition (which is possible), the testbench
will hang, forever polling the ready signal.

I have tried to develop a timeout scheme that will limit the number of
operating clock cycles that the testbench will wait for the ready
signal, before it abandons the wait and moves on with the stimulus. I
have not been succesful.

The easiest/cleanest way to accomplish this is to check the

ready_signal with a clock instead of waiting for an edge of it ie:

@(posedge clk) begin
if (!ready_signal) timer <= timer + 1;
if (ready_signal | (timer > expired)) ->do_sim;
end

@(do_sim) continue_simulation;

I have tried a down-counter scheme in parallel with the line of code
above in a fork-join statement. However, the fork-join will only
finish when both forks are complete, so this will not help me. I can
develop a count-down scheme fine, but in the event that the "end of
the count" is reached, I am unsure how to "skip" the @(posedge) line
above.

One way to do what you want here is:

fork
begin : wait_block
@(posedge ready_signal) disable wait_block;
@expired disable wait_block;
join

you also need an external event called expired which counts the number
of clocks and gets triggered. This way fork/join terminates by either
event happening (ie posedge ready_signal or expired).
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

On Aug 22, 5:22 pm, SB <paulsheeha...@yahoo.com> wrote:

I have tried a down-counter scheme in parallel with the line of code
above in a fork-join statement.  However, the fork-join will only
finish when both forks are complete, so this will not help me.  I can
develop a count-down scheme fine, but in the event that the "end of
the count" is reached, I am unsure how to "skip" the @(posedge) line
above.

A common way to do this is to use the Verilog "disable" construct to
kill the waiting subprocess. For example,

fork: myblock
@(posedge ready_signal) do something;
#timeout disable myblock;
join

Or for your case, where you want to wait for some number of clocks,
and your "do something" is to continue executing the next statement,
perhaps

fork: myblock
@(posedge ready_signal) disable myblock;
begin
repeat (num_clocks)
@(posedge clk) ;
complain about the timeout or do whatever else you wanted to do
if it happened
disable myblock;
end
join
continue executing