Help with switch debouncing

Guest
I am trying to debounce a switch on a Xilinx FPGA using Verilog
modules. The main module is a shift register with a load and enable,
and the register should shift each time the button is pressed. I am
using the clock to debounce the switch. The problem i am having with
my design is that each time i push the button, the register shifts a
lot (more than 8 times, the number of LEDs i have on the board.)
could someone help me out with this? Thanks.

-Keith

// shiftrne.v

module shiftrne (R, L, E, w, BTN, Q, clock);

parameter n = 8;
input clock;
input [n-1:0] R;
input L, E, w, BTN;
output [n-1:0] Q;
reg [n-1:0] Q;
integer k;
wire btn2;

//assign btn2 = BTN;

mydebounce M1 (clock, BTN, btn2);

always @(btn2)
if(btn2 == 1)
begin

if (L)
Q <= R;
else if (!E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;

end
end
endmodule

-----------------------------------------------------------------------------------------------------------------------------------------

module mydebounce (clock, butin, butout);

parameter DELAY = 270000; // .01 sec with a 27Mhz clock
input clock, butin;
output butout;

reg [18:0] count;
reg butout;

//assign butout <= butin;

always @(posedge clock)

if (butin == 1)
begin
count <= count+1;
if (count == DELAY)
butout <= 1;
else
butout <= 0;
end
else
begin
count <= 0;
butout <= 0;
end
 
Do you have an SPDT switch? Check out Peter Alfke's Six Easy Pieces for the
simple switch debounce.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy

I've seen a 50 ms value used for decbouncing in the past. When you see your
switch active, start a counter. Assert your switch detect once and ignore
any further switch transitions until the count reaches 50 ms worth of your
clock cycles. If the switch is not yet released, wait until it's released
to disarm the circuit. For a switch that only bounces when engaged rather
than when released, this works for your needs. I'll use SPDT switches for
all my FPGA pushbuttons as long as I can get away with it.

- John_H


<HannumK@gmail.com> wrote in message
news:1175203306.110375.301590@l77g2000hsb.googlegroups.com...
I am trying to debounce a switch on a Xilinx FPGA using Verilog
modules. The main module is a shift register with a load and enable,
and the register should shift each time the button is pressed. I am
using the clock to debounce the switch. The problem i am having with
my design is that each time i push the button, the register shifts a
lot (more than 8 times, the number of LEDs i have on the board.)
could someone help me out with this? Thanks.

-Keith

// shiftrne.v

module shiftrne (R, L, E, w, BTN, Q, clock);

parameter n = 8;
input clock;
input [n-1:0] R;
input L, E, w, BTN;
output [n-1:0] Q;
reg [n-1:0] Q;
integer k;
wire btn2;

//assign btn2 = BTN;

mydebounce M1 (clock, BTN, btn2);

always @(btn2)
if(btn2 == 1)
begin

if (L)
Q <= R;
else if (!E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;

end
end
endmodule

-----------------------------------------------------------------------------------------------------------------------------------------

module mydebounce (clock, butin, butout);

parameter DELAY = 270000; // .01 sec with a 27Mhz clock
input clock, butin;
output butout;

reg [18:0] count;
reg butout;

//assign butout <= butin;

always @(posedge clock)

if (butin == 1)
begin
count <= count+1;
if (count == DELAY)
butout <= 1;
else
butout <= 0;
end
else
begin
count <= 0;
butout <= 0;
end
Click to expand...
 
On Mar 29, 7:19 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
Do you have an SPDT switch? Check out Peter Alfke's Six Easy Pieces for the
simple switch debounce.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy

I've seen a 50 ms value used for decbouncing in the past. When you see your
switch active, start a counter. Assert your switch detect once and ignore
any further switch transitions until the count reaches 50 ms worth of your
clock cycles. If the switch is not yet released, wait until it's released
to disarm the circuit. For a switch that only bounces when engaged rather
than when released, this works for your needs. I'll use SPDT switches for
all my FPGA pushbuttons as long as I can get away with it.

- John_H

Hann...@gmail.com> wrote in message

news:1175203306.110375.301590@l77g2000hsb.googlegroups.com...



I am trying to debounce a switch on a Xilinx FPGA using Verilog
modules. The main module is a shift register with a load and enable,
and the register should shift each time the button is pressed. I am
using the clock to debounce the switch. The problem i am having with
my design is that each time i push the button, the register shifts a
lot (more than 8 times, the number of LEDs i have on the board.)
could someone help me out with this? Thanks.

-Keith

// shiftrne.v

module shiftrne (R, L, E, w, BTN, Q, clock);

parameter n = 8;
input clock;
input [n-1:0] R;
input L, E, w, BTN;
output [n-1:0] Q;
reg [n-1:0] Q;
integer k;
wire btn2;

//assign btn2 = BTN;

mydebounce M1 (clock, BTN, btn2);

always @(btn2)
if(btn2 == 1)
begin

if (L)
Q <= R;
else if (!E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;

end
end
endmodule

---------------------------------------------------------------------------­--------------------------------------------------------------

module mydebounce (clock, butin, butout);

parameter DELAY = 270000; // .01 sec with a 27Mhz clock
input clock, butin;
output butout;

reg [18:0] count;
reg butout;

//assign butout <= butin;

always @(posedge clock)

if (butin == 1)
begin
count <= count+1;
if (count == DELAY)
butout <= 1;
else
butout <= 0;
end
else
begin
count <= 0;
butout <= 0;
end- Hide quoted text -

- Show quoted text -
Click to expand...
Its actually not a switch, i mistyped it originally. It is a
pushbutton like you were talking about. Your method is what i am
trying to find out if my code does. I want it to look for 270000
"highs" on the input and pass 1 high to my shift register. Its not
working and i dont know why.
 
On Mar 29, 5:34 pm, Hann...@gmail.com wrote:
On Mar 29, 7:19 pm, "John_H" <newsgr...@johnhandwork.com> wrote:



Do you have an SPDT switch? Check out Peter Alfke's Six Easy Pieces for the
simple switch debounce.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy

I've seen a 50 ms value used for decbouncing in the past. When you see your
switch active, start a counter. Assert your switch detect once and ignore
any further switch transitions until the count reaches 50 ms worth of your
clock cycles. If the switch is not yet released, wait until it's released
to disarm the circuit. For a switch that only bounces when engaged rather
than when released, this works for your needs. I'll use SPDT switches for
all my FPGA pushbuttons as long as I can get away with it.

- John_H

Hann...@gmail.com> wrote in message

news:1175203306.110375.301590@l77g2000hsb.googlegroups.com...

I am trying to debounce a switch on a Xilinx FPGA using Verilog
modules. The main module is a shift register with a load and enable,
and the register should shift each time the button is pressed. I am
using the clock to debounce the switch. The problem i am having with
my design is that each time i push the button, the register shifts a
lot (more than 8 times, the number of LEDs i have on the board.)
could someone help me out with this? Thanks.

-Keith

// shiftrne.v

module shiftrne (R, L, E, w, BTN, Q, clock);

parameter n = 8;
input clock;
input [n-1:0] R;
input L, E, w, BTN;
output [n-1:0] Q;
reg [n-1:0] Q;
integer k;
wire btn2;

//assign btn2 = BTN;

mydebounce M1 (clock, BTN, btn2);

always @(btn2)
if(btn2 == 1)
begin

if (L)
Q <= R;
else if (!E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;

end
end
endmodule

---------------------------------------------------------------------------­--------------------------------------------------------------

module mydebounce (clock, butin, butout);

parameter DELAY = 270000; // .01 sec with a 27Mhz clock
input clock, butin;
output butout;

reg [18:0] count;
reg butout;

//assign butout <= butin;

always @(posedge clock)

if (butin == 1)
begin
count <= count+1;
if (count == DELAY)
butout <= 1;
else
butout <= 0;
end
else
begin
count <= 0;
butout <= 0;
end- Hide quoted text -

- Show quoted text -

Its actually not a switch, i mistyped it originally. It is a
pushbutton like you were talking about. Your method is what i am
trying to find out if my code does. I want it to look for 270000
"highs" on the input and pass 1 high to my shift register. Its not
working and i dont know why.
Click to expand...
What happens when the count is equal to DELAY+1?

David Walker
 
Switch is a mechanical system. A mechanical system can have vibrations
on touch surface,
which will generate 0-1-0-1-0 transitions until the stable value.
In this case your "else" code will be triggered a lot.

Debouncing is done with FSMs. Implement a FSM made up of the same
counter "count[18:0]".
The counter must be triggered during the 1st switch event, and must
stay in the counting state.
At the end of count state, check the the value again.

Utku.

On 30 Mrz., 19:44, "dbwalker0...@gmail.com" <dbwalker0...@gmail.com>
wrote:
On Mar 29, 5:34 pm, Hann...@gmail.com wrote:



On Mar 29, 7:19 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

Do you have an SPDT switch? Check out Peter Alfke's Six Easy Pieces for the
simple switch debounce.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy

I've seen a 50 ms value used for decbouncing in the past. When you see your
switch active, start a counter. Assert your switch detect once and ignore
any further switch transitions until the count reaches 50 ms worth of your
clock cycles. If the switch is not yet released, wait until it's released
to disarm the circuit. For a switch that only bounces when engaged rather
than when released, this works for your needs. I'll use SPDT switches for
all my FPGA pushbuttons as long as I can get away with it.

- John_H

Hann...@gmail.com> wrote in message

news:1175203306.110375.301590@l77g2000hsb.googlegroups.com...

I am trying to debounce a switch on a Xilinx FPGA using Verilog
modules. The main module is a shift register with a load and enable,
and the register should shift each time the button is pressed. I am
using the clock to debounce the switch. The problem i am having with
my design is that each time i push the button, the register shifts a
lot (more than 8 times, the number of LEDs i have on the board.)
could someone help me out with this? Thanks.

-Keith

// shiftrne.v

module shiftrne (R, L, E, w, BTN, Q, clock);

parameter n = 8;
input clock;
input [n-1:0] R;
input L, E, w, BTN;
output [n-1:0] Q;
reg [n-1:0] Q;
integer k;
wire btn2;

//assign btn2 = BTN;

mydebounce M1 (clock, BTN, btn2);

always @(btn2)
if(btn2 == 1)
begin

if (L)
Q <= R;
else if (!E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;

end
end
endmodule

---------------------------------------------------------------------------­­--------------------------------------------------------------

module mydebounce (clock, butin, butout);

parameter DELAY = 270000; // .01 sec with a 27Mhz clock
input clock, butin;
output butout;

reg [18:0] count;
reg butout;

//assign butout <= butin;

always @(posedge clock)

if (butin == 1)
begin
count <= count+1;
if (count == DELAY)
butout <= 1;
else
butout <= 0;
end
else
begin
count <= 0;
butout <= 0;
end- Hide quoted text -

- Show quoted text -

Its actually not a switch, i mistyped it originally. It is a
pushbutton like you were talking about. Your method is what i am
trying to find out if my code does. I want it to look for 270000
"highs" on the input and pass 1 high to my shift register. Its not
working and i dont know why.

What happens when the count is equal to DELAY+1?

David Walker
Click to expand...
 
On Mar 30, 8:34 am, Hann...@gmail.com wrote:
I am trying to debounce a switch on a Xilinx FPGA using Verilog
modules. The main module is a shift register with a load and enable,
and the register should shift each time the button is pressed. I am
using the clock to debounce the switch. The problem i am having with
my design is that each time i push the button, the register shifts a
lot (more than 8 times, the number of LEDs i have on the board.)
could someone help me out with this? Thanks.

-Keith


Its actually not a switch, i mistyped it originally. It is a
pushbutton like you were talking about. Your method is what i am
trying to find out if my code does. I want it to look for 270000
"highs" on the input and pass 1 high to my shift register. Its not
working and i dont know why.
"not working" in what manner? Asserting too many times?
Click to expand...

Possibly, what you should be doing on the input is to use a oneshot
multivibrator followed by a rising edge detector (or falling edge, if
you prefer to do the action on release). Like so:
/*oneshot multivibrator*/
reg [31:0] counter;
always @(posedge clk, negedge reset_n) if(!reset_n) counter <= 0; else
begin
if(butin) counter <= DELAY;
else if(counter != 0) counter <= counter - 1; end
/*cleansed remains high as long as the counter hasn't counted down to
zero.
As long as the switch is pressed, counter remains at DELAY, which is
any
value other than zero. If bouncing happens within the DELAY time, it
simply resets the counter, but doesn't cause cleansed to change.
*/
wire cleansed = counter != 0;

/*edge detect*/
/*raise butout only on the rising edge of cleansed.*/
reg d_cleansed;
always @(posedge clk) begin
d_cleansed <= cleansed; end
wire butout = cleansed == 1 && d_cleansed == 0;

Also, currently in your design, if count == {19{1'b1}}, it will wrap
around to 0, and restart counting at 0, 1, 2... this is probably your
problem too.

Lastly, since the input is an external input, and this input happens
not to have any assurances as to timing, your input might actually
change at such a time that it will violate the hold/setup time of your
process/FPGA's register. You might want to add two synchronizing
registers prior to actually getting the input. This reduces
metastability. Some boards and FPGA's may have them built-in,
however.
 
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