Help with $setuphold syntax

[Paul Richardson]

Greetings, I have the following line in an sd file
SETUPHOLD (COND I9_cond D ) (COND I9_cond (posedge CK) ) (0.183974:0.
197958:0.197958) (-0.097690:-0.090224:-0.090224))

This is the line I use in a library element:
$setuphold(posedge CK &&& (I9_cond == 1), D &&& (I9_cond == 1), tsetup_
negedge$D$CK, thold_negedge$D$CK, NOTIFIER);

Unfortunately the back annotation does not believe these two to be
a match and therefore does not back annotate the design

Can anyone out there, looking at the sdf line, describe the
corresponding line which should be present in the verilog model

thanks in advance

 

[David Roberts]

On Thu, 13 Nov 2003 20:17:05 +0000, Paul Richardson wrote:

Greetings, I have the following line in an sd file
SETUPHOLD (COND I9_cond D ) (COND I9_cond (posedge CK) ) (0.183974:0.
197958:0.197958) (-0.097690:-0.090224:-0.090224))

This is the line I use in a library element:
$setuphold(posedge CK &&& (I9_cond == 1), D &&& (I9_cond == 1), tsetup_
negedge$D$CK, thold_negedge$D$CK, NOTIFIER);

Unfortunately the back annotation does not believe these two to be
a match and therefore does not back annotate the design

Can anyone out there, looking at the sdf line, describe the
corresponding line which should be present in the verilog model

thanks in advance

Actually what you have are two different things. Either change you SDF
file to be
(SETUPHOLD D (posedge CK) (0.183974:0.197958:0.197958)
(-0.097690:-0.090224:-0.090224) (SCOND I9_cond ==1) (CCOND == 1))

or you want you remove the "== 1" from the HDL

$setuphold(posedge CK &&& I9_cond, D &&& I9_cond, tsetup_negedge$D$CK,
thold_negedge$D$CK, NOTIFIER);

--David Roberts