Help with selfcheck TB

[BM]

Hi,
I am trying to learn some Verilog and VHDL coding. For this purpose I have started with an Ripple ADDER in VHDL which I am testing using a Verilog Testbech. The outputs from the ADDER are registered and it is controlled by Reset and Enable signals.

I have a problem when I try to self check the module. for the situation when reset = 0 and en = 0 , the selfcheck process still on and returns erroneous values. So I tried to add the enable signal to t sensitivity list of the always loop but then Vivado compiler complains with an error

Any suggestions to solve this issue?
Should the @ ( en = '1') work?

See the code below:

// Init & Test En
initial begin
$display("----------------------\n %d Bit Full-Adder\n----------------------\n", MODULES);
// Initialization of stimulus
in1 = 0; in2 = 0; cy_in = 0; clk= 0; en = 0; rst = 1;
#PERIOD rst = 0;
#(PERIOD*3) en = 1;
end

// Clock signal generation
always
#(PERIOD/2) clk = ~clk;

//Asyn process with input stimulus
always begin // this gives an error code compiler --> @(en = '1') begin
for ( i=0; i < LOOP; i = i + 1 ) begin
for (b=0; b < LOOP; b = b + 1) begin
in1 = i;
in2 = b;
count_comp = in1 + in2;
#PERIOD;
count = {carry, sum};
if (count != count_comp) begin
$display ("Error at time %d", $time);
$display ("Expected value: %d, Value calculated: %d", count_comp, count);
end
end
end
end


Ooutput from the Tcl console:
---------------------
4 Bit Full-Adder
----------------------

Error at time 20
Expected value: 1, Value calculated: 0
Error at time 30
Expected value: 2, Value calculated: 0
Error at time 40