J
James
Guest
I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees. I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes. I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option. Can someone please help me out? I currently have the
following which may or may not be correct:
create_generated_clock \
-name my_new_clock \
-divide_by 2 \
-edges { 1 3 5 } \ <-- also divides the clock by 2, so the
divide_by option is not really necessary
-edge_shift { 1 1 1 } \ <-- not really sure about this part ...
wondering if this is correct
-source [get_pins source_clock] \
[get_nets {new_clock}]
I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly. Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.
The best documentation I can find with Google is on Altera's site.
http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html#note1
The site provides the following example:
# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift 0 5 0 } [get_registers clkdivB|clkreg]
The above example corresponds to Figure 2 on the linked web page. I
don't entirely understand this example or how the edge_shift is {0 5
0}. It would be great if someone could explain that as well.
Thanks for any help.
James
the frequency of the source clock and also phase shifted by 90
degrees. I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes. I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option. Can someone please help me out? I currently have the
following which may or may not be correct:
create_generated_clock \
-name my_new_clock \
-divide_by 2 \
-edges { 1 3 5 } \ <-- also divides the clock by 2, so the
divide_by option is not really necessary
-edge_shift { 1 1 1 } \ <-- not really sure about this part ...
wondering if this is correct
-source [get_pins source_clock] \
[get_nets {new_clock}]
I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly. Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.
The best documentation I can find with Google is on Altera's site.
http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html#note1
The site provides the following example:
# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift 0 5 0 } [get_registers clkdivB|clkreg]
The above example corresponds to Figure 2 on the linked web page. I
don't entirely understand this example or how the edge_shift is {0 5
0}. It would be great if someone could explain that as well.
Thanks for any help.
James