Help with SDC (specifically edge_shift)

J

James

Guest
I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees. I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes. I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option. Can someone please help me out? I currently have the
following which may or may not be correct:

create_generated_clock \
-name my_new_clock \
-divide_by 2 \
-edges { 1 3 5 } \ <-- also divides the clock by 2, so the
divide_by option is not really necessary
-edge_shift { 1 1 1 } \ <-- not really sure about this part ...
wondering if this is correct
-source [get_pins source_clock] \
[get_nets {new_clock}]

I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly. Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.


The best documentation I can find with Google is on Altera's site.
http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html#note1
The site provides the following example:

# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift 0 5 0 } [get_registers clkdivB|clkreg]

The above example corresponds to Figure 2 on the linked web page. I
don't entirely understand this example or how the edge_shift is {0 5
0}. It would be great if someone could explain that as well.

Thanks for any help.
James
 
On Apr 5, 3:53 pm, James <jmos1...@gmail.com> wrote:
I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees.  I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes.  I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option.  Can someone please help me out?  I currently have the
following which may or may not be correct:

create_generated_clock \
    -name my_new_clock \
    -divide_by 2 \
    -edges { 1 3 5 } \   <-- also divides the clock by 2, so the
divide_by option is not really necessary
    -edge_shift { 1 1 1 } \  <-- not really sure about this part ....
wondering if this is correct
    -source [get_pins source_clock] \
            [get_nets {new_clock}]

I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly.  Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.

The best documentation I can find with Google is on Altera's site.http://www.altera.com/support/software/timequest/clock/tq-generate-cl...
The site provides the following example:

# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift  0 5 0 } [get_registers clkdivB|clkreg]

The above example corresponds to Figure 2 on the linked web page.  I
don't entirely understand this example or how the edge_shift is {0 5
0}.  It would be great if someone could explain that as well.

Thanks for any help.
James
The SDC constraints can be used to describe timing relationships (as
well as other design constraints such as placement locations) for use
by the timing analyzer. They cannot be used to drive the tools to
create a physical clock condition as it appears you are attempting.

You should use the clocking wizard in CoreGen as a starting point.

Ed McGettigan
--
Xilinx Inc.
 
On Apr 6, 11:53 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Apr 5, 3:53 pm, James <jmos1...@gmail.com> wrote:









I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees.  I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes.  I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option.  Can someone please help me out?  I currently have the
following which may or may not be correct:

create_generated_clock \
    -name my_new_clock \
    -divide_by 2 \
    -edges { 1 3 5 } \   <-- also divides the clock by 2, so the
divide_by option is not really necessary
    -edge_shift { 1 1 1 } \  <-- not really sure about this part ....
wondering if this is correct
    -source [get_pins source_clock] \
            [get_nets {new_clock}]

I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly.  Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.

The best documentation I can find with Google is on Altera's site.http://www.altera.com/support/software/timequest/clock/tq-generate-cl...
The site provides the following example:

# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift  0 5 0 } [get_registers clkdivB|clkreg]

The above example corresponds to Figure 2 on the linked web page.  I
don't entirely understand this example or how the edge_shift is {0 5
0}.  It would be great if someone could explain that as well.

Thanks for any help.
James

The SDC constraints can be used to describe timing relationships (as
well as other design constraints such as placement locations) for use
by the timing analyzer.  They cannot be used to drive the tools to
create a physical clock condition as it appears you are attempting.

You should use the clocking wizard in CoreGen as a starting point.

Ed McGettigan
--
Xilinx Inc.
Ed,
Thanks for the response. I'm actually using a set of UCF constraints
for the implementation. However, I still need to run a timing
analysis with the newer SDC timing analyzer. In my UCF, I use "PHASE
+ X ns" in my TIMESPEC for a 90 degree phase shift. I'm trying to
determine the equivalent constraint in the SDC format, but I cannot
find any worthwhile documentation on edge_shift.

Anyone else have any documentation they can point me to?

Thanks.
 
On Apr 6, 12:00 pm, James <jmos1...@gmail.com> wrote:
On Apr 6, 11:53 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Apr 5, 3:53 pm, James <jmos1...@gmail.com> wrote:

I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees.  I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes.  I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option.  Can someone please help me out?  I currently have the
following which may or may not be correct:

create_generated_clock \
    -name my_new_clock \
    -divide_by 2 \
    -edges { 1 3 5 } \   <-- also divides the clock by 2, so the
divide_by option is not really necessary
    -edge_shift { 1 1 1 } \  <-- not really sure about this part ...
wondering if this is correct
    -source [get_pins source_clock] \
            [get_nets {new_clock}]

I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly.  Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.

The best documentation I can find with Google is on Altera's site.http://www.altera.com/support/software/timequest/clock/tq-generate-cl...
The site provides the following example:

# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift  0 5 0 } [get_registers clkdivB|clkreg]

The above example corresponds to Figure 2 on the linked web page.  I
don't entirely understand this example or how the edge_shift is {0 5
0}.  It would be great if someone could explain that as well.

Thanks for any help.
James

The SDC constraints can be used to describe timing relationships (as
well as other design constraints such as placement locations) for use
by the timing analyzer.  They cannot be used to drive the tools to
create a physical clock condition as it appears you are attempting.

You should use the clocking wizard in CoreGen as a starting point.

Ed McGettigan
--
Xilinx Inc.

Ed,
Thanks for the response.  I'm actually using a set of UCF constraints
for the implementation.  However, I still need to run a timing
analysis with the newer SDC timing analyzer.  In my UCF, I use "PHASE
+ X ns" in my TIMESPEC for a 90 degree phase shift.  I'm trying to
determine the equivalent constraint in the SDC format, but I cannot
find any worthwhile documentation on edge_shift.

Anyone else have any documentation they can point me to?

Thanks.- Hide quoted text -

- Show quoted text -
This is a constraint that I am not familar with. After a quick
examination of the constraint documentation (UCF) I do see the use of
PHASE along with PERIOD. This should be applied automatically to the
clock outputs from a PLL or DCM with just a PERIOD constraint on the
input to the PLL or DCM.

You said that you were using UCF to implement the design. I can
understand using UCF to constrain the design for timing analyzer, but
not for implementing.

Can you please describe the clocking topology for this design and
which FPGA family you are using?

Ed McGettigan
--
Xilinx Inc.
 

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