Help with Pmod VGA on Altera

[Rick C. Hodgin]

I have a Cyclone V GX Starter kit board, with Quartus 13.1:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=830

I'd like some help on setting this up to get a Pmod VGA device
to generate proper timing for VGA modes up to a 150 MHz pixel
clock (1680 x 1050).

The Pmod VGA device:
https://store.digilentinc.com/pmod-vga-video-graphics-array/

It has 4-bits each for R,G,B, and 2-bits for hsync and vsync.
The timings for VGA video modes can be found here, along with
the polarity of the hysync and vsync signals:
http://tinyvga.com/vga-timing

My primary goals are to support these modes and to get my VGA
monitor to recognize the signal:

640 x 480
800 x 600
1024 x 768
1280 x 1024
1680 x 1050

I'm content to draw alternating red, green, blue bars of about
16 pixels each, interspaced with black and white squares. Just
something to show an image.

My goal is to get two of these devices working simultaneously
on the FPGA, and to setup the ability to read RAM for the pixels.
I wouldn't even mind supporting a monochrome output for now to
be honest. I just want to be get the displays up and running
and I can add-on from there.

-----
Would anyone like to help me with this project? I'm looking for
someone to help me with the Verilog code, and to go through the
steps in Quartus to get it to synthesize and update the FPGA. I
don't have test equipment, so if someone can use their test equip-
ment to help me in that area it would be appreciated too. I fig-
ure we can share code. I'll write what I think it should be (I
already have it written), and someone can help guide me where I
am wrong, or where the idea / design is incomplete. Plus, all of
the aspects of getting it to work with an FPGA.

The GX Starter Kit also has a built-in HDMI if someone would like
to help me with that instead.

Thank you in advance.

--
Rick C. Hodgin

 

On Friday, December 7, 2018 at 5:09:46 PM UTC-6, Rick C. Hodgin wrote:

I have a Cyclone V GX Starter kit board, with Quartus 13.1:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=830

I'd like some help on setting this up to get a Pmod VGA device
to generate proper timing for VGA modes up to a 150 MHz pixel
clock (1680 x 1050).

The Pmod VGA device:
https://store.digilentinc.com/pmod-vga-video-graphics-array/

It has 4-bits each for R,G,B, and 2-bits for hsync and vsync.
The timings for VGA video modes can be found here, along with
the polarity of the hysync and vsync signals:
http://tinyvga.com/vga-timing

My primary goals are to support these modes and to get my VGA
monitor to recognize the signal:

640 x 480
800 x 600
1024 x 768
1280 x 1024
1680 x 1050

I'm content to draw alternating red, green, blue bars of about
16 pixels each, interspaced with black and white squares. Just
something to show an image.

My goal is to get two of these devices working simultaneously
on the FPGA, and to setup the ability to read RAM for the pixels.
I wouldn't even mind supporting a monochrome output for now to
be honest. I just want to be get the displays up and running
and I can add-on from there.

-----
Would anyone like to help me with this project? I'm looking for
someone to help me with the Verilog code, and to go through the
steps in Quartus to get it to synthesize and update the FPGA. I
don't have test equipment, so if someone can use their test equip-
ment to help me in that area it would be appreciated too. I fig-
ure we can share code. I'll write what I think it should be (I
already have it written), and someone can help guide me where I
am wrong, or where the idea / design is incomplete. Plus, all of
the aspects of getting it to work with an FPGA.

The GX Starter Kit also has a built-in HDMI if someone would like
to help me with that instead.

Thank you in advance.

--
Rick C. Hodgin

]>I'm looking for someone to help me with the Verilog code, and to go through the steps in Quartus to get it to synthesize and update the FPGA.

The Cyclone V GX Starter kit has an installed demo using the HDMI port. Its Verilog source code is at Terasic. Edit source code until you get what you want (e.g. incremental development). However, there is a lot of source code to examine.

The Digilent Pmod VGA device has VHDL source code demo and timings for different rasters. However the GX Starter kit does not have Pmod connectors so one must use jumper wires to connect the Starter kit to the VGA Pmod board.. And edit the pin constraints to match.

At a more basic level there are Altera/Intel tutorials:
https://www.intel.com/content/www/us/en/programmable/support/training/university/materials-tutorials.html
Suspect that this is where you need to start?

 

[Rick C. Hodgin]

>I'm looking for someone to help me with the Verilog code, and to go through the steps in Quartus to get it to synthesize and update the FPGA.

The Cyclone V GX Starter kit has an installed demo using the HDMI port. Its Verilog source code is at Terasic. Edit source code until you get what you want (e.g. incremental development). However, there is a lot of source code to examine.

Can you point me to a link. I saw the video on YouTube that they went through, but it involved a lot of little comments about things that I didn't understand. They are tool-related, and design-implementation-in-FPGA related.. I could really use someone to take me through the process and help me understand what's required of the tool to make it work.

The Digilent Pmod VGA device has VHDL source code demo and timings for different rasters. However the GX Starter kit does not have Pmod connectors so one must use jumper wires to connect the Starter kit to the VGA Pmod board. And edit the pin constraints to match.

At a more basic level there are Altera/Intel tutorials:
https://www.intel.com/content/www/us/en/programmable/support/training/university/materials-tutorials.html
Suspect that this is where you need to start?

I can try. I think I need help using the tool. It's difficult for me to enter into new tools and other ways of thinking due to dyslexia and the difficulties I have in reading certain types of technology books / tutorials / etc.

--
Rick C. Hodgin

 

[Emilian Miron]

Sample code for doing VGA with simple I/O:
https://www.fpga4fun.com/PongGame.html

The support page of the board you linked to has resources including an HDMI demo:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830&PartNo=4

For using the tools, the old Altera website had great instructional videos. This seems to be the new Intel branded page:
https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/support.html

Good luck!

 

[Rick C. Hodgin]

On Monday, December 10, 2018 at 1:56:03 PM UTC-5, Emilian Miron wrote:

Sample code for doing VGA with simple I/O:
https://www.fpga4fun.com/PongGame.html

The support page of the board you linked to has resources including an HDMI demo:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830&PartNo=4

For using the tools, the old Altera website had great instructional videos. This seems to be the new Intel branded page:
https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/support.html

Good luck!

Thank you, Emilian. I will check them out. I've looked at the videos before, and I'm still not sure I get it. I think I need someone to help me over TeamViewer + voice chat or something. Just enough to answer what are some probably very basic questions, but they are show-stoppers / blockers for me today.

In the meantime...

A friend of mine has me working on a Scott CPU emulator at present. My design has a built-in single-step debugger, and emulates the Scott CPU from the book "But How Do It Know?" by J. Clark Scott. That CPU is a real, functional, simple 8-bit CPU with less than 40 instructions encoding about 220 single-byte opcodes with variations, limited I/O, and uses 256 bytes of RAM:

http://www.buthowdoitknow.com/cpu_model_intro.html

This person is a professional CPU designer since the 70s, and he wants me to complete my work and send him a copy of my code and design. He said he'd do the same and then send me his copy. We'd look them over and compare notes with our approaches, designs, thoughts, extensions, how we implemented various things, etc.

I think he's using it as a teaching tool because he's told me how he designs things on paper and in emulators rather than in hardware. He came up with this design after I told him I was devoting development time to my Logician tool. I think he's worried about me. But, I can already design and write emulators. I'm looking now to move my designs into real hardware.

--
Rick C. Hodgin

 

[Rick C. Hodgin]

On Tuesday, December 11, 2018 at 5:58:43 PM UTC-5, Rick C. Hodgin wrote:

In the meantime...

A friend of mine has me working on a Scott CPU emulator at present. My design has a built-in single-step debugger, and emulates the Scott CPU from the book "But How Do It Know?" by J. Clark Scott. That CPU is a real, functional, simple 8-bit CPU with less than 40 instructions encoding about 220 single-byte opcodes with variations, limited I/O, and uses 256 bytes of RAM:

http://www.buthowdoitknow.com/cpu_model_intro.html

If anyone's interested, here's the project:
http://www.libsf.org:8990/projects/LIB/repos/libsf/browse/hardware/scottcpu/emulator

http://www.libsf.org:8990/projects/LIB/repos/libsf/browse/hardware/scottcpu/emulator/scott_cpu_emulator.png

To build and test it:
c:\> git clone http://www.libsf.org:8990/scm/lib/libsf.git
Cloning into libsf...
c:\> cd hardware\scottcpu\emulator\
c:\hardware\scottcpu\emulator\> dir *.*

You can load the emulator.sln file in Visual Studio 2008 or later. Load the Debug build profile. Rebuild and press F5 to run. In the emulator:

F10: Single step
F5: Run
F2: Toggle I/O registers
F3: Toggle GP registers
F4: Toggle Output/RAM
Ctrl+F5: Reset

You can also arrow around and input hex values only. If interested, Please report any bugs. It may lock up if you press F5 and your program doesn't have a termination point. Haven't tested that yet. It will also lock up if it doesn't terminate on a JMP self instruction, like:

@@:
jmp @b

--
Rick C. Hodgin