help with oneshot please

M

Mike Shonle

Guest
Hi, I'm just starting out in VHDL, and I'm trying to make an asynchronously
triggered oneshot that gets triggered by a short positive pulse and then
sets the output high for 10 clock cycles and then resets itself. Here's
what I have so far, which never sets the output high. Any help or advice
greatly appreciated. Thanks.

entity oneshot is
port ( clock : in std_logic;
trigger : in std_logic;
pulse : out std_logic);
end oneshot;


architecture BEHAVIORAL of oneshot is
signal triggered: integer range 0 to 1;
signal count: integer range 0 to 10; -- count variable
begin
process (trigger,clock)
begin
-- wait for trigger to go high
if trigger = '1' then
triggered <= 1;
count <= 10;
pulse <= '1';
elsif clock'event and clock = '1' then
if triggered = 1 and count > 0 then
pulse <= '1';
elsif count = 0 then
triggered <=0;
pulse <= '0';
else
count <= count -1;
end if;
end if;
end process;
end BEHAVIORAL;
 
Hi Mike,

Hi, I'm just starting out in VHDL, and I'm trying to make an asynchronously
triggered oneshot that gets triggered by a short positive pulse and then
sets the output high for 10 clock cycles and then resets itself. Here's
what I have so far, which never sets the output high. Any help or advice
greatly appreciated. Thanks.
Click to expand...
There may some problems with your design.
- the design will not start to count down until after trigger goes
low. This may be intentional though.
- it has some issues wrt meta-stability: usually, you want to
synchronize the trigger event by double clocking it before feeding it
into the synchronous logic. In it's current form, you may get an
undefined state when deasserting trigger coincides with the rising
edge of the clock. This may lead to an undefined state.

This being said, I don't really see why pulse doesn't become high when
trigger is asserted...
Can you show us the testbench that drives this module?

Tom Verbeure


entity oneshot is
port ( clock : in std_logic;
trigger : in std_logic;
pulse : out std_logic);
end oneshot;


architecture BEHAVIORAL of oneshot is
signal triggered: integer range 0 to 1;
signal count: integer range 0 to 10; -- count variable
begin
process (trigger,clock)
begin
-- wait for trigger to go high
if trigger = '1' then
triggered <= 1;
count <= 10;
pulse <= '1';
elsif clock'event and clock = '1' then
if triggered = 1 and count > 0 then
pulse <= '1';
elsif count = 0 then
triggered <=0;
pulse <= '0';
else
count <= count -1;
end if;
end if;
end process;
end BEHAVIORAL;
Click to expand...
 
Mike Shonle a écrit:
Hi, I'm just starting out in VHDL, and I'm trying to make an asynchronously
triggered oneshot that gets triggered by a short positive pulse and then
sets the output high for 10 clock cycles and then resets itself. Here's
what I have so far, which never sets the output high. Any help or advice
greatly appreciated. Thanks.
Click to expand...
I don't see why the output doesn't go high but I can see a problem with
the counter: it will never count down.
After the trigger pulse, triggered = '1' and count > 0 so your first
condition is met. And in this case your code doesn't do anything but
seeting pulse high. count will remain greater than 0, triggered will
remain high...
I would write:

if count > 0 then
pulse <= '1';
count <= count - 1;
else
pulse <= '0';
end if;

No need for the 'triggered' signal.



entity oneshot is
port ( clock : in std_logic;
trigger : in std_logic;
pulse : out std_logic);
end oneshot;


architecture BEHAVIORAL of oneshot is
signal triggered: integer range 0 to 1;
signal count: integer range 0 to 10; -- count variable
begin
process (trigger,clock)
begin
-- wait for trigger to go high
if trigger = '1' then
triggered <= 1;
count <= 10;
pulse <= '1';
elsif clock'event and clock = '1' then
if triggered = 1 and count > 0 then
pulse <= '1';
elsif count = 0 then
triggered <=0;
pulse <= '0';
else
count <= count -1;
end if;
end if;
end process;
end BEHAVIORAL;
Click to expand...
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Thanks everyone for your help. I did end up getting it working -- the
reason it wasn't setting 'pulse' high was that the VHDL model wasn't even
assigned to the part! (did I mention that I'm just starting out? And that
Xilinx tools are a pain?). Now it seems to be ok, I'm using the following:

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity oneshot is
port ( clock : in std_logic;
trigger : in std_logic;
pulse : out std_logic);
end oneshot;


architecture BEHAVIORAL of oneshot is
signal count: integer range 0 to 10; -- count variable
begin
process (trigger,clock)
begin
-- wait for trigger leading edge
if trigger = '1' then
count <= 10;
elsif clock'event and clock = '1' then
if count > 0 then
pulse <= '1';
count <= count - 1;
else
pulse <= '0';
end if;
end if;
end process;
end BEHAVIORAL;

-- synopsys translate_off
configuration CFG_oneshot of oneshot is
for BEHAVIORAL
end for;
end CFG_oneshot;
-- synopsys translate_on






"Mike Shonle" <mike@psychonic.net> wrote in message
news:RrucndkCdJBssFLdRWPC-w@speakeasy.net...
Hi, I'm just starting out in VHDL, and I'm trying to make an
asynchronously
triggered oneshot that gets triggered by a short positive pulse and then
sets the output high for 10 clock cycles and then resets itself. Here's
what I have so far, which never sets the output high. Any help or advice
greatly appreciated. Thanks.

entity oneshot is
port ( clock : in std_logic;
trigger : in std_logic;
pulse : out std_logic);
end oneshot;


architecture BEHAVIORAL of oneshot is
signal triggered: integer range 0 to 1;
signal count: integer range 0 to 10; -- count variable
begin
process (trigger,clock)
begin
-- wait for trigger to go high
if trigger = '1' then
triggered <= 1;
count <= 10;
pulse <= '1';
elsif clock'event and clock = '1' then
if triggered = 1 and count > 0 then
pulse <= '1';
elsif count = 0 then
triggered <=0;
pulse <= '0';
else
count <= count -1;
end if;
end if;
end process;
end BEHAVIORAL;
Click to expand...
 
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