Help with H-Bridge

[Big Matt]

I have put together a h-bridge circuit for use in a radio control car,
and was hoping that someone could have a look at it for me. I am worried
that I am likely to blow the thing up The circuit is here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)

The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will
insure that only one side of the bridge comes on, and if the transistor
inverter will be a suitable inverter.

Also, is the fuse ok? (Is it likely to save the FETS in the event that I
do stuff up?)


Many, many thanks,

Big Matt

 

[Terry Given]

Big Matt wrote:

I have put together a h-bridge circuit for use in a radio control car,
and was hoping that someone could have a look at it for me. I am worried
that I am likely to blow the thing up The circuit is here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)

it will blow up the first time you try to use it :{

there are no base resistors on any of the bipolar transistors. When Q5
turns ON, it pulls the base of PNP Q6 to 0V. But the emitter is
connected to +7V, so a great deal of current will flow, leading to the
destruction of the pnp, probably followed by the NPN.

the logic outputs wont like driving into a base-emitter junction very
much either, and may break. A smattering of (say) 1k base resistors
would cure that.

the single-ended FET drive is set up to give fast turn on and slow (via
1k only) turn off of all 4 FETs, which is exactly the opposite of what
is generally required, and usually results in shoot-thru current (both
FETs on for a little bit). If the shoot-thru period is long, the FETs
expire rapidly. If its short, then the high peak power dissipation
(7V^2/(2*Rdson)) during shoot-thru averages out to a
not-so-destructively-high value, and the FET runs hotter than you expect
- often hot enough to make it fail in 5-10 minutes (depends on thermal
time constant of heatsink). low switching frequency reduces the average
power.

Deadtime is often used to solve this problem - a brief (adjustable)
period during which both FETs are off.

why not run the 4073 from the +7V supply, and let it level-shift the
0-5V micro outputs to 0-7V. A few gates paralleled ought to be able to
directly drive your FETs (I havent looked at the fet data though)....

the FETs wont like the 10nF caps much if Fswitch is high

The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will
insure that only one side of the bridge comes on, and if the transistor
inverter will be a suitable inverter.

learn to use base resistors. 4000-series CMOS is happy to run up to 12V
or more, why not use a real inverter?

that being said, I have a design that uses a BC847BPN as a +12V
push-pull inverter with a 70ns propagation delay, and we've made 20,000
of them....

the AND gates are a good start, but dead-time is really required to
prevent shoot-thru (aka cross-conduction).

Also, is the fuse ok? (Is it likely to save the FETS in the event that I
do stuff up?)

put a cap *directly* across the supply of your H-bridge, the fuse must
not be between the cap and the FETs. the idea is to reduce the
inductance from the cap to the FET bridge.

the fuse itself is unlikely to protect your FETs. Check the fuse I^2t
figure against I^2t for the FET (Ifsm can be used to figure out I^2t).
The smallest I^2t blows first, and is usually the FET. But the fuse will
prevent a fire.

I never build this type of circuit without pulse-by-pulse current limiting.

Many, many thanks,

Big Matt

Cheers
Terry

 

[Andrew M]

I'd say the turn-off time could cause a dissipation problem due to slow switching and
the cross-conduction currents. If yuo could insert some deadtime that would help
(separate drive for upper and lower FETs on each leg).

-Andrew M

"Big Matt" <no_email@sorry.com> wrote in message
news:1121938186.184562@news.pip.com.au...

I have put together a h-bridge circuit for use in a radio control car, and was hoping
that someone could have a look at it for me. I am worried that I am likely to blow
the thing up The circuit is here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)

The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will insure that only
one side of the bridge comes on, and if the transistor inverter will be a suitable
inverter.

Also, is the fuse ok? (Is it likely to save the FETS in the event that I do stuff
up?)


Many, many thanks,

Big Matt

 

[Big Matt]

Terry Given wrote:

Big Matt wrote:

I have put together a h-bridge circuit for use in a radio control car,
and was hoping that someone could have a look at it for me. I am
worried that I am likely to blow the thing up The circuit is here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)


it will blow up the first time you try to use it :{

there are no base resistors on any of the bipolar transistors. When Q5
turns ON, it pulls the base of PNP Q6 to 0V. But the emitter is
connected to +7V, so a great deal of current will flow, leading to the
destruction of the pnp, probably followed by the NPN.

the logic outputs wont like driving into a base-emitter junction very
much either, and may break. A smattering of (say) 1k base resistors
would cure that.

Bad habit on my part I'm afraid. I always tend to omit the base
resistors when drawing circuits (I guess it is a bit obvious to me that
they should be there), and tend to put them in when I draw up the pcb.
It is a habit that will one day cause me to burn my house down. I will
kick myself for you. Twice. Hard.

the single-ended FET drive is set up to give fast turn on and slow (via
1k only) turn off of all 4 FETs, which is exactly the opposite of what
is generally required, and usually results in shoot-thru current (both
FETs on for a little bit). If the shoot-thru period is long, the FETs
expire rapidly. If its short, then the high peak power dissipation
(7V^2/(2*Rdson)) during shoot-thru averages out to a
not-so-destructively-high value, and the FET runs hotter than you expect
- often hot enough to make it fail in 5-10 minutes (depends on thermal
time constant of heatsink). low switching frequency reduces the average
power.

Deadtime is often used to solve this problem - a brief (adjustable)
period during which both FETs are off.

Could I implement deadtime into my micro code? Or this that asking for
trouble? Would it be possible to somehow monitoring the bridge to ensure
that it is off before switching the other side on, maybe through the
spare and gate or directly to the micro? Incidentally, what is a
suitably safe dead time period?

why not run the 4073 from the +7V supply, and let it level-shift the
0-5V micro outputs to 0-7V. A few gates paralleled ought to be able to
directly drive your FETs (I havent looked at the fet data though)....

According to the data sheet the 4073 is able to source about 1-2 mA. If
I use 3 gates in parallel that is only 6 mA. If I were to reduce the
pullup/down resistors to say 50 ohms, would that be better? 50 ohms
would give me about 100 mA Ic current, 33 ohms would give me about 150
mA, which is still below the maximum 200 mA allowed by the data sheet.

There is also a space issue as well. I really don't want to use 3 4073
chips if I can get away with a couple of transistors.

the FETs wont like the 10nF caps much if Fswitch is high

I included them only because they came with the motor and that is the

recommended configuration. I don't have them on my current forward only
single fet control, so I will scrap them here as well.

The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will
insure that only one side of the bridge comes on, and if the
transistor inverter will be a suitable inverter.


learn to use base resistors. 4000-series CMOS is happy to run up to 12V
or more, why not use a real inverter?

Space was my primary concern. I don't have much room to play with, and
it seemed a bit wasteful to include six inverters and only use one. I
trust this is ok?

that being said, I have a design that uses a BC847BPN as a +12V
push-pull inverter with a 70ns propagation delay, and we've made 20,000
of them....

the AND gates are a good start, but dead-time is really required to
prevent shoot-thru (aka cross-conduction).


Also, is the fuse ok? (Is it likely to save the FETS in the event that
I do stuff up?)


put a cap *directly* across the supply of your H-bridge, the fuse must
not be between the cap and the FETs. the idea is to reduce the
inductance from the cap to the FET bridge.

the fuse itself is unlikely to protect your FETs. Check the fuse I^2t
figure against I^2t for the FET (Ifsm can be used to figure out I^2t).
The smallest I^2t blows first, and is usually the FET. But the fuse will
prevent a fire.

I don't seem to be able to find that data on jaycar's website. I
(naively) assumed that since the fets could handle 40 a, that a 10a fuse
would blow before the fets. If that is not the case, then I will just
scarp the fuse idea altogether. Frankly, if I can't save the fets the
whole thing may as well burn

I never build this type of circuit without pulse-by-pulse current limiting.



Many, many thanks,

Big Matt


Cheers
Terry

Thanks again for your time, I actually feel I am starting to understand
(some) of it.

Big Matt

 

[Big Matt]

Andrew M wrote:

I'd say the turn-off time could cause a dissipation problem due to slow switching and
the cross-conduction currents. If yuo could insert some deadtime that would help
(separate drive for upper and lower FETs on each leg).

I understand what you mean about the deadtime. What would you suggest to
be a suitable period for this?

Also, are you suggesting that I drive each of the four fets
individually? I had actually considered this, as it would allow me to
implement a crude braking system by turning on both the bottom fets, but
dismissed it because it seemed to make the possibility of shorting the
fets more likely. Perhaps I should reconsider?

Thanks for your time,

Big Matt

-Andrew M

"Big Matt" <no_email@sorry.com> wrote in message
news:1121938186.184562@news.pip.com.au...

I have put together a h-bridge circuit for use in a radio control car, and was hoping
that someone could have a look at it for me. I am worried that I am likely to blow
the thing up The circuit is here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)

The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will insure that only
one side of the bridge comes on, and if the transistor inverter will be a suitable
inverter.

Also, is the fuse ok? (Is it likely to save the FETS in the event that I do stuff
up?)


Many, many thanks,

Big Matt

 

[Terry Given]

Hi Matt,

Big Matt wrote:

Terry Given wrote:

Big Matt wrote:

I have put together a h-bridge circuit for use in a radio control
car, and was hoping that someone could have a look at it for me. I am
worried that I am likely to blow the thing up The circuit is here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)



it will blow up the first time you try to use it :{

there are no base resistors on any of the bipolar transistors. When Q5
turns ON, it pulls the base of PNP Q6 to 0V. But the emitter is
connected to +7V, so a great deal of current will flow, leading to the
destruction of the pnp, probably followed by the NPN.

the logic outputs wont like driving into a base-emitter junction very
much either, and may break. A smattering of (say) 1k base resistors
would cure that.


Bad habit on my part I'm afraid. I always tend to omit the base
resistors when drawing circuits (I guess it is a bit obvious to me that
they should be there), and tend to put them in when I draw up the pcb.
It is a habit that will one day cause me to burn my house down. I will
kick myself for you. Twice. Hard.

OK

the single-ended FET drive is set up to give fast turn on and slow
(via 1k only) turn off of all 4 FETs, which is exactly the opposite of
what is generally required, and usually results in shoot-thru current
(both FETs on for a little bit). If the shoot-thru period is long, the
FETs expire rapidly. If its short, then the high peak power
dissipation (7V^2/(2*Rdson)) during shoot-thru averages out to a
not-so-destructively-high value, and the FET runs hotter than you
expect - often hot enough to make it fail in 5-10 minutes (depends on
thermal time constant of heatsink). low switching frequency reduces
the average power.

Deadtime is often used to solve this problem - a brief (adjustable)
period during which both FETs are off.


Could I implement deadtime into my micro code? Or this that asking for
trouble? Would it be possible to somehow monitoring the bridge to ensure
that it is off before switching the other side on, maybe through the
spare and gate or directly to the micro? Incidentally, what is a
suitably safe dead time period?

you can put dead-time in your software, but what happens if the software
flips out? one solution is to make sure the software works. The same 55W
smsp that uses the little inverter has dead-time done with schmitt
triggers, series R's with diodes across them and shunt C's. Take a pulse
Q, generate its complement /Q. Feed both Q and /Q into identical R//D C
circuits, followed by schmitt triggers (to square the waveform up again)
giving Y and /Y. Now the RC circuit sets the turn-on delay for both Y
and /Y. The diodes ensure the turn-off delay is small. Voila, deadtime.

look at the time constants of charging and discharging the gates, along
with Vth, to figure out the required deadtime, then add a suitable
safety margin. Or look at a pair of gate voltages with a dual-trace
scope, and make sure one FET is completely off (Vg = 0V) before the
other one begins to turn on.

do you know how to do the RC calculations?

why not run the 4073 from the +7V supply, and let it level-shift the
0-5V micro outputs to 0-7V. A few gates paralleled ought to be able to
directly drive your FETs (I havent looked at the fet data though)....


According to the data sheet the 4073 is able to source about 1-2 mA. If
I use 3 gates in parallel that is only 6 mA. If I were to reduce the
pullup/down resistors to say 50 ohms, would that be better? 50 ohms
would give me about 100 mA Ic current, 33 ohms would give me about 150
mA, which is still below the maximum 200 mA allowed by the data sheet.

fair call re. 4073. Its not uncommon to use 6 inverters paralleled to
drive a small FET though.

what you find with your single-ended gatedrive is that speeding it up
comes at a heavy price - 50R will dissipate 7V^2/50 = 1W which is quite
a bit!

try a complementary emitter follower after your (now level-shifting) 4073:

-----+------- +7V
|c
|/
+--| npn
| |\ e
[4073]--[Rbase]-+ +-----[Rgate]--- to FET
| |/ e
+--| pnp
|\ c
|
-----+------- 0V

A BC547/557 combo ought to do you a few hundred milliamps, BC327/337
about an amp. use the base resistor though.

beware the voltage drop though - VGmin = Vol + Vbe. The CMOS gate will
pull pretty close to 0V, so the output voltage will swing from 0.6V to
6.4V or so. If Vth is real low this can be a problem, but for your FET
its about 2V, so this is fine.

There is also a space issue as well. I really don't want to use 3 4073
chips if I can get away with a couple of transistors.

SMT, use a BC847BPN dual npn + pnp in a 6-leg SOT323 (smaller than
SOT23) Better get a microscope though.....

the FETs wont like the 10nF caps much if Fswitch is high

I included them only because they came with the motor and that is the
recommended configuration. I don't have them on my current forward only
single fet control, so I will scrap them here as well.



The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will
insure that only one side of the bridge comes on, and if the
transistor inverter will be a suitable inverter.


learn to use base resistors. 4000-series CMOS is happy to run up to
12V or more, why not use a real inverter?


Space was my primary concern. I don't have much room to play with, and
it seemed a bit wasteful to include six inverters and only use one. I
trust this is ok?

its fine. but without a speedup cap across the base resistor it wont be
very fast.

that being said, I have a design that uses a BC847BPN as a +12V
push-pull inverter with a 70ns propagation delay, and we've made
20,000 of them....

the AND gates are a good start, but dead-time is really required to
prevent shoot-thru (aka cross-conduction).


Also, is the fuse ok? (Is it likely to save the FETS in the event
that I do stuff up?)



put a cap *directly* across the supply of your H-bridge, the fuse must
not be between the cap and the FETs. the idea is to reduce the
inductance from the cap to the FET bridge.

the fuse itself is unlikely to protect your FETs. Check the fuse I^2t
figure against I^2t for the FET (Ifsm can be used to figure out I^2t).
The smallest I^2t blows first, and is usually the FET. But the fuse
will prevent a fire.


I don't seem to be able to find that data on jaycar's website. I
(naively) assumed that since the fets could handle 40 a, that a 10a fuse
would blow before the fets. If that is not the case, then I will just
scarp the fuse idea altogether. Frankly, if I can't save the fets the
whole thing may as well burn

you wont.

http://www.remcomplekt.ru/datasheet/trz/IRFZ44.PDF

Idm is 200A, which is a repetitive peak current (rep rate governed by
temp rise). so its a fairly big FET. If they gave a single-shot current
rating I^2t falls out directly from that number.

you also wont be able to find any I^2t data for your fuse either

if you were keen, you could ascertain the fuse wire size, and make a
stab at I^2t based on adiabatic heating (no heat transfer) and the
melting point of the metal (make a guess....)

in practice, use the smallest fuse that the equipment reliably operates
with. dont use a fuse at more than 60% of its rated current, or it may
fail due to thermal fatigue.

it probably doesnt matter if your circuit burns, but the building its
housed in is another story.....


you may also want to ensure that fried FETs dont snot the micro - a
simple series R (1-10k) can suffice there. Unless the micro is a lot
cheaper than the FETs, in which case who cares.

I never build this type of circuit without pulse-by-pulse current
limiting.



Many, many thanks,

Big Matt



Cheers
Terry


Thanks again for your time, I actually feel I am starting to understand
(some) of it.

Big Matt

Cheers
Terry

 

[Big Matt]

Terry Given wrote:

Hi Matt,

Big Matt wrote:

Terry Given wrote:

Big Matt wrote:

I have put together a h-bridge circuit for use in a radio control
car, and was hoping that someone could have a look at it for me. I
am worried that I am likely to blow the thing up The circuit is
here:

http://www.cheapanet.com.au/~mattcad/hb.gif (~13k)

or, if you prefer in pdf:

http://www.cheapanet.com.au/~mattcad/hb.pdf (~27k)




it will blow up the first time you try to use it :{

there are no base resistors on any of the bipolar transistors. When
Q5 turns ON, it pulls the base of PNP Q6 to 0V. But the emitter is
connected to +7V, so a great deal of current will flow, leading to
the destruction of the pnp, probably followed by the NPN.

the logic outputs wont like driving into a base-emitter junction very
much either, and may break. A smattering of (say) 1k base resistors
would cure that.



Bad habit on my part I'm afraid. I always tend to omit the base
resistors when drawing circuits (I guess it is a bit obvious to me
that they should be there), and tend to put them in when I draw up the
pcb. It is a habit that will one day cause me to burn my house down. I
will kick myself for you. Twice. Hard.


OK


the single-ended FET drive is set up to give fast turn on and slow
(via 1k only) turn off of all 4 FETs, which is exactly the opposite
of what is generally required, and usually results in shoot-thru
current (both FETs on for a little bit). If the shoot-thru period is
long, the FETs expire rapidly. If its short, then the high peak power
dissipation (7V^2/(2*Rdson)) during shoot-thru averages out to a
not-so-destructively-high value, and the FET runs hotter than you
expect - often hot enough to make it fail in 5-10 minutes (depends on
thermal time constant of heatsink). low switching frequency reduces
the average power.

Deadtime is often used to solve this problem - a brief (adjustable)
period during which both FETs are off.



Could I implement deadtime into my micro code? Or this that asking for
trouble? Would it be possible to somehow monitoring the bridge to
ensure that it is off before switching the other side on, maybe
through the spare and gate or directly to the micro? Incidentally,
what is a suitably safe dead time period?


you can put dead-time in your software, but what happens if the software
flips out? one solution is to make sure the software works. The same 55W
smsp that uses the little inverter has dead-time done with schmitt
triggers, series R's with diodes across them and shunt C's. Take a pulse
Q, generate its complement /Q. Feed both Q and /Q into identical R//D C
circuits, followed by schmitt triggers (to square the waveform up again)
giving Y and /Y. Now the RC circuit sets the turn-on delay for both Y
and /Y. The diodes ensure the turn-off delay is small. Voila, deadtime.

look at the time constants of charging and discharging the gates, along
with Vth, to figure out the required deadtime, then add a suitable
safety margin. Or look at a pair of gate voltages with a dual-trace
scope, and make sure one FET is completely off (Vg = 0V) before the
other one begins to turn on.

do you know how to do the RC calculations?


why not run the 4073 from the +7V supply, and let it level-shift the
0-5V micro outputs to 0-7V. A few gates paralleled ought to be able
to directly drive your FETs (I havent looked at the fet data though)....



According to the data sheet the 4073 is able to source about 1-2 mA.
If I use 3 gates in parallel that is only 6 mA. If I were to reduce
the pullup/down resistors to say 50 ohms, would that be better? 50
ohms would give me about 100 mA Ic current, 33 ohms would give me
about 150 mA, which is still below the maximum 200 mA allowed by the
data sheet.


fair call re. 4073. Its not uncommon to use 6 inverters paralleled to
drive a small FET though.

what you find with your single-ended gatedrive is that speeding it up
comes at a heavy price - 50R will dissipate 7V^2/50 = 1W which is quite
a bit!

try a complementary emitter follower after your (now level-shifting) 4073:

-----+------- +7V
|c
|/
+--| npn
| |\ e
[4073]--[Rbase]-+ +-----[Rgate]--- to FET
| |/ e
+--| pnp
|\ c
|
-----+------- 0V

A BC547/557 combo ought to do you a few hundred milliamps, BC327/337
about an amp. use the base resistor though.

beware the voltage drop though - VGmin = Vol + Vbe. The CMOS gate will
pull pretty close to 0V, so the output voltage will swing from 0.6V to
6.4V or so. If Vth is real low this can be a problem, but for your FET
its about 2V, so this is fine.

There is also a space issue as well. I really don't want to use 3 4073
chips if I can get away with a couple of transistors.


SMT, use a BC847BPN dual npn + pnp in a 6-leg SOT323 (smaller than
SOT23) Better get a microscope though.....


the FETs wont like the 10nF caps much if Fswitch is high

I included them only because they came with the motor and that is the
recommended configuration. I don't have them on my current forward
only single fet control, so I will scrap them here as well.



The PWM signal is being generated by a PIC micro.

Specifically I would like to know if the use of the AND gates will
insure that only one side of the bridge comes on, and if the
transistor inverter will be a suitable inverter.


learn to use base resistors. 4000-series CMOS is happy to run up to
12V or more, why not use a real inverter?



Space was my primary concern. I don't have much room to play with, and
it seemed a bit wasteful to include six inverters and only use one. I
trust this is ok?


its fine. but without a speedup cap across the base resistor it wont be
very fast.


that being said, I have a design that uses a BC847BPN as a +12V
push-pull inverter with a 70ns propagation delay, and we've made
20,000 of them....

the AND gates are a good start, but dead-time is really required to
prevent shoot-thru (aka cross-conduction).


Also, is the fuse ok? (Is it likely to save the FETS in the event
that I do stuff up?)




put a cap *directly* across the supply of your H-bridge, the fuse
must not be between the cap and the FETs. the idea is to reduce the
inductance from the cap to the FET bridge.

the fuse itself is unlikely to protect your FETs. Check the fuse I^2t
figure against I^2t for the FET (Ifsm can be used to figure out
I^2t). The smallest I^2t blows first, and is usually the FET. But the
fuse will prevent a fire.



I don't seem to be able to find that data on jaycar's website. I
(naively) assumed that since the fets could handle 40 a, that a 10a
fuse would blow before the fets. If that is not the case, then I will
just scarp the fuse idea altogether. Frankly, if I can't save the fets
the whole thing may as well burn


you wont.

http://www.remcomplekt.ru/datasheet/trz/IRFZ44.PDF

Idm is 200A, which is a repetitive peak current (rep rate governed by
temp rise). so its a fairly big FET. If they gave a single-shot current
rating I^2t falls out directly from that number.

you also wont be able to find any I^2t data for your fuse either

if you were keen, you could ascertain the fuse wire size, and make a
stab at I^2t based on adiabatic heating (no heat transfer) and the
melting point of the metal (make a guess....)

in practice, use the smallest fuse that the equipment reliably operates
with. dont use a fuse at more than 60% of its rated current, or it may
fail due to thermal fatigue.

it probably doesnt matter if your circuit burns, but the building its
housed in is another story.....


you may also want to ensure that fried FETs dont snot the micro - a
simple series R (1-10k) can suffice there. Unless the micro is a lot
cheaper than the FETs, in which case who cares.


I never build this type of circuit without pulse-by-pulse current
limiting.



Many, many thanks,

Big Matt




Cheers
Terry



Thanks again for your time, I actually feel I am starting to
understand (some) of it.

Big Matt


Cheers
Terry

Thanks for the detailed info Terry. I will take all your suggestions on
board and come up with a revised circuit in a few days. If it is alright
with everyone, I will post that up in a new thread, or if if you prefer
I will stick it on the end of this one. I am not sure what the group's
policy is on that?

Many thanks again

Big Matt

 

[Terry Given]

Big Matt wrote:
[snip]

I will stick it on the end of this one. I am not sure what the group's
policy is on that?

Thats brave, asking usenet where to stick it...

Cheers
Terry