help with generating ten dig. signals

[Ned Brush]

Hello,
I'm trying to generate roughly 10 digital signals that mimic a state
machine output. They are inputs to a custom mixed-signal design that
I'm simulating. I've tried implementing it in AHDL (SpectreHDL) using a
global counter variable to determine signal values. It works, but it is
extremely slow and simulations take a long time to run. Is there a
quicker/cleaner way to do this?

Thanks in advance,
Ned

 

[Svenn Are Bjerkem]

Ned Brush wrote:

Hello,
I'm trying to generate roughly 10 digital signals that mimic a state
machine output. They are inputs to a custom mixed-signal design that
I'm simulating. I've tried implementing it in AHDL (SpectreHDL) using a
global counter variable to determine signal values. It works, but it is
extremely slow and simulations take a long time to run. Is there a
quicker/cleaner way to do this?

When you say that your solution is extremely slow, could you show some code?

If you only generate digital signals that are used as control signals in
your analog testbench you could do something like this (some initial work):
1. Use Verilog to generate your fsm output and use $monitor to put signals
to file.
2. Write a script (perl,python,tcl,ruby,whatever) to convert that dump to
pwl sources in a file
V1 (fsm1 0) vsource pwl=[...]
V2 (fsm2 0) vsource pwl=[...]
3. Place signal labeis in your schematic that fits the source naming in the
pwl source file.
4. Include that pwl file in Analog artist through the Model include dialog.

As I said, this is a bit initial work, (you have to write that verilog, and
that script) but after a while the effort will pay off as you can check a
lot of states and do changes quickly.
--
Svenn